Multi-Residue Two-Step Incremental ADC. - Faraz Adin; Hanyu Wang; Lukang Shi; Rajiv Singh; Erhan Hancioglu; Gabor C. Temes (MWSCAS, 2024)

Wideband Low-Distortion Noise-Coupled Delta-Sigma ADC. - Hanyu Wang; Faraz Adin; Un-Ku Moon; Gabor C. Temes (MWSCAS, 2024)

A 16 GΩ Input Impedance Amplifier with Flicker Noise Reduction for Neural Recording Applications. - Jyotindra R. Shakya; Gabor C. Temes; Faraz Adin (CICC, 2025)

An 89.5 dB SNDR 500 kHz BW Largely Passive Fourth-Order Noise-Coupled Delta-Sigma Modulator. - Hanyu Wang; Faraz Adin; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

98-dB SNDR Multi-Residue Two-Step Incremental ADC With Two-Capacitor SAR. - Faraz Adin; Hanyu Wang; Lukang Shi; Rajiv Singh; Erhan Hancioglu; Gabor C. Temes (IEEE Trans. Circuits Syst. II Express Briefs, 2025)