A high performance processor architecture for multimedia applications. - Shafqat Khan; Muhammad Rashid 001; Faraz Javaid (Comput. Electr. Eng., 2018)

A configurable high resolution digital pixel readout integrated circuit with on-chip image processing. - Faraz Javaid; Muhammad Rashid 001; Shafqat Khan (Comput. Electr. Eng., 2020)