A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support. - Alok Baluni; Farhad Merchant; S. K. Nandy 001; Srinivasan Balakrishnan (ISED, 2011)

Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. - Zoltán Endre Rákossy; Farhad Merchant; Axel Acosta-Aponte; S. K. Nandy 001; Anupam Chattopadhyay (ASAP, 2014)

Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. - Mahesh Mahadurkar; Farhad Merchant; Arka Maity; Kapil Vatwani; Ishan Munje; Nandhini Gopalan; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2014)

Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. - Zoltán Endre Rákossy; Farhad Merchant; Axel Acosta-Aponte; S. K. Nandy 001; Anupam Chattopadhyay (VLSI-SoC, 2014)

Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). - Farhad Merchant; Anupam Chattopadhyay; Ganesh Garga; S. K. Nandy 001; Ranjani Narayan; Nandhini Gopalan (VLSID, 2014)

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. - Saptarsi Das; Kavitha T. Madhu; Madhav Krishna; Nalesh Sivanandan; Farhad Merchant; Santhi Natarajan; Ipsita Biswas; Adithya Pulli; S. K. Nandy 001; Ranjani Narayan (J. Syst. Archit., 2014)

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. - Farhad Merchant; Arka Maity; Mahesh Mahadurkar; Kapil Vatwani; Ishan Munje; Madhava Krishna C; Nalesh Sivanandan; Nandhini Gopalan; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (VLSID, 2015)

Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays. - Debjyoti Bhattacharjee; Farhad Merchant; Anupam Chattopadhyay (VLSI-SoC, 2016)

Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. - Farhad Merchant; Nimash Choudhary; S. K. Nandy 001; Ranjani Narayan (VLSID, 2016)

Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (VLSID, 2016)

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (CoRR, 2016)

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. - Farhad Merchant; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (Parallel Process. Lett., 2017)

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (ARC, 2018)

Parameterized Posit Arithmetic Hardware Generator. - Rohit Chaurasiya; John L. Gustafson; Rahul Shrestha; Jonathan Neudorfer; Sangeeth Nambiar; Kaustav Niyogi; Farhad Merchant; Rainer Leupers (ICCD, 2018)

Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan; Rainer Leupers (CoRR, 2018)

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (IEEE Trans. Parallel Distributed Syst., 2018)

Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. - Dominik Sisejkovic; Farhad Merchant; Rainer Leupers; Gerd Ascheid; Sascha Kegreiss (ETS, 2019)

Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. - Dominik Sisejkovic; Farhad Merchant; Rainer Leupers; Gerd Ascheid; Sascha Kegreiss (ACM Great Lakes Symposium on VLSI, 2019)

Protecting the Integrity of Processor Cores with Logic Encryption. - Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (SoCC, 2019)

A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. - Dominik Sisejkovic; Farhad Merchant; Rainer Leupers; Gerd Ascheid; Volker Kiefer (VLSI-DAT, 2019)

A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan; Rainer Leupers (VLSID, 2019)

Applying Modified Householder Transform to Kalman Filter. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan; Rainer Leupers (VLSID, 2019)

Scaling Logic Locking Schemes to Multi-module Hardware Designs. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers; Sascha Kegreiß (ARCS, 2020)

Next Generation Arithmetic for Edge Computing. - Andre Guntoro; Cecilia De la Parra; Farhad Merchant; Florent de Dinechin; John L. Gustafson; Martin Langhammer; Rainer Leupers; Sangeeth Nambiar (DATE, 2020)

A secure hardware-software solution based on RISC-V, logic locking and microkernel. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers; Massimiliano Giacometti; Sascha Kegreiß (SCOPES, 2020)

Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit. - Jure Vreca; Karl J. X. Sturm; Ernest Gungl; Farhad Merchant; Paolo Bientinesi; Rainer Leupers; Zmago Brezocnik (IEEE Access, 2020)

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. - Riya Jain; Niraj N. Sharma; Farhad Merchant; Sachin B. Patkar; Rainer Leupers (CoRR, 2020)

Nano Security: From Nano-Electronics to Secure Systems. - Ilia Polian; Frank Altmann; Tolga Arul; Christian Boit; Ralf Brederlow; Lucas Davi; Rolf Drechsler; Nan Du 004; Thomas Eisenbarth 001; Tim Güneysu; Sascha Hermann; Matthias Hiller; et al. (DATE, 2021)

Vertical IP Protection of the Next-Generation Devices: Quo Vadis? - Shubham Rai; Siddharth Garg; Christian Pilato; Vladimir Herdt; Elmira Moussavi; Dominik Sisejkovic; Ramesh Karri; Rolf Drechsler; Farhad Merchant; Akash Kumar 001 (DATE, 2021)

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. - Lennart M. Reimann; Luca Hanel; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (ICCD, 2021)

Brightening the Optical Flow through Posit Arithmetic. - Vinay Saxena; Ankitha Reddy; Jonathan Neudorfer; John L. Gustafson; Sangeeth Nambiar; Rainer Leupers; Farhad Merchant (ISQED, 2021)

Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. - Dominik Sisejkovic; Lennart M. Reimann; Elmira Moussavi; Farhad Merchant; Rainer Leupers (VLSI-SoC, 2021)

An Investigation on Inherent Robustness of Posit Data Representation. - Ihsen Alouani; Anouar Ben Khalifa; Farhad Merchant; Rainer Leupers (VLSID, 2021)

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. - Farhad Merchant; Dominik Sisejkovic; Lennart M. Reimann; Kirthihan Yasotharan; Thomas Grass; Rainer Leupers (VLSID, 2021)

ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems. - Suresh Nambi; Salim Ullah; Siva Satyendra Sahoo; Aditya Lohana; Farhad Merchant; Akash Kumar 001 (IEEE Access, 2021)

Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Harshit Srivastava; Ahmed Hallawa; Rainer Leupers (ACM J. Emerg. Technol. Comput. Syst., 2021)

NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. - Melvin Galicia; Stephan Menzel; Farhad Merchant; Maximilian Müller; Hsin-Yu Chen; Qing-Tai Zhao; Felix Cüppers; Abdur R. Jalil; Qi Shu; Peter Schüffelgen; Gregor Mussler; Carsten Funck; et al. (DATE, 2022)

NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. - Felix Staudigl; Hazem Al Indari; Daniel Schön; Dominik Sisejkovic; Farhad Merchant; Jan Moritz Joseph; Vikas Rana; Stephan Menzel; Rainer Leupers (DATE, 2022)

pHGen: A pH-Based Key Generation Mechanism Using ISFETs. - Elmira Moussavi; Dominik Sisejkovic; Fabian Brings; Daniyar Kizatov; Animesh Singh; Xuan Thang Vu; Rainer Leupers; Sven Ingebrandt; Vivek Pachauri; Farhad Merchant (HOST, 2022)

A Parallel SystemC Virtual Platform for Neuromorphic Architectures. - Melvin Galicia; Farhad Merchant; Rainer Leupers (ISQED, 2022)

Discrete Steps towards Approximate Computing. - Michael Gansen; Jie Lou; Florian Freye; Tobias Gemmeke; Farhad Merchant; Albert Zeyer; Mohammad Zeineldeen; Ralf Schlüter; Xin Fan 002 (ISQED, 2022)

Security as an Important Ingredient in Neuromorphic Engineering. - Farhad Merchant (ISVLSI, 2022)

A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. - Elmira Moussavi; Dominik Sisejkovic; Animesh Singh; Daniyar Kizatov; Rainer Leupers; Sven Ingebrandt; Vivek Pachauri; Farhad Merchant (LATS, 2022)

PA-PUF: A Novel Priority Arbiter PUF. - Simranjeet Singh; Srinivasu Bodapati; Sachin B. Patkar; Rainer Leupers; Anupam Chattopadhyay; Farhad Merchant (VLSI-SoC, 2022)

A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security. - Felix Staudigl; Farhad Merchant; Rainer Leupers (IEEE Des. Test, 2022)

Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. - Simranjeet Singh; Furqan Zahoor; Gokulnath Rajendran; Sachin B. Patkar; Anupam Chattopadhyay; Farhad Merchant (ASP-DAC, 2023)

DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking. - Anand Raj; Nikhitha Avula; Pabitra Das; Dominik Sisejkovic; Farhad Merchant; Amit Acharyya (ISCAS, 2023)

IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. - Omar Ghazal; Simranjeet Singh; Tousif Rahman; Shengqi Yu; Yujin Zheng; Domenico Balsamo; Sachin B. Patkar; Farhad Merchant; Fei Xia 001; Alex Yakovlev; Rishad A. Shafik (ISLPED, 2023)

Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. - Simranjeet Singh; Elmira Moussavi; Christopher Bengel; Sachin B. Patkar; Rainer Waser; Rainer Leupers; Vikas Rana; Vivek Pachauri; Stephan Menzel; Farhad Merchant (NANOARCH, 2023)

Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. - Elmira Moussavi; Animesh Singh; Dominik Sisejkovic; Aravind Padma Kumar; Daniyar Kizatov; Sven Ingebrandt; Rainer Leupers; Vivek Pachauri; Farhad Merchant (NEWCAS, 2023)

Finite State Automata Design using 1T1R ReRAM Crossbar. - Simranjeet Singh; Omar Ghazal; Chandan Kumar Jha 001; Vikas Rana; Rolf Drechsler; Rishad A. Shafik; Alex Yakovlev; Sachin B. Patkar; Farhad Merchant (NEWCAS, 2023)

Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. - Simranjeet Singh; Furqan Zahoor; Gokulnath Rajendran; Vikas Rana; Sachin B. Patkar; Anupam Chattopadhyay; Farhad Merchant (NEWCAS, 2023)

PR-PUF: A Reconfigurable Strong RRAM PUF. - Gokulnath Rajendran; Furqan Zahoor; Simranjeet Singh; Farhad Merchant; Vikas Rana; Anupam Chattopadhyay (VLSI-SoC, 2023)

Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow's Advanced Memory Range Feature. - Lennart M. Reimann; Jonathan Wiesner; Karol Jaszczyk; Chiara Ghinami; Dominik Germek; Farhad Merchant; Rainer Leupers (VLSI-SoC (Selected Papers), 2023)

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. - Lennart M. Reimann; Jonathan Wiesner; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (VLSI-SoC, 2023)

CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. - Niraj N. Sharma; Riya Jain; Mohana Madhumita Pokkuluri; Sachin B. Patkar; Rainer Leupers; Rishiyur S. Nikhil; Farhad Merchant (J. Syst. Archit., 2023)

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. - Simranjeet Singh; Chandan Kumar Jha 001; Ankit Bende; Phrangboklang Lyngton Thangkhiew; Vikas Rana; Sachin B. Patkar; Rolf Drechsler; Farhad Merchant (IEEE Embed. Syst. Lett., 2023)

FPGA-based Deep Learning Inference Accelerators: Where Are We Standing? - Anouar Nechi; Lukas Groth; Saleh Mulhem; Farhad Merchant; Rainer Buchty; Mladen Berekovic (ACM Trans. Reconfigurable Technol. Syst., 2023)

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. - Simranjeet Singh; Chandan Kumar Jha 001; Ankit Bende; Vikas Rana; Sachin B. Patkar; Rolf Drechsler; Farhad Merchant (ASPDAC, 2024)

Error Detection and Correction Codes for Safe In-Memory Computations. - Luca Parrini; Taha Soliman; Benjamin Hettwer; Jan Micha Borrmann; Simranjeet Singh; Ankit Bende; Vikas Rana; Farhad Merchant; Norbert Wehn (ETS, 2024)

In-Memory Mirroring: Cloning Without Reading. - Simranjeet Singh; Ankit Bende; Chandan Kumar Jha 001; Vikas Rana; Rolf Drechsler; Sachin B. Patkar; Farhad Merchant (VLSI-SoC, 2024)

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. - Ankit Bende; Simranjeet Singh; Chandan Kumar Jha 001; Tim Kempen; Felix Cüppers; Christopher Bengel; Andre Zambanini; Dennis Nielinger; Sachin B. Patkar; Rolf Drechsler; Rainer Waser; Farhad Merchant; et al. (VLSID, 2024)

Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG. - Gokulnath Rajendran; Furqan Zahoor; Sidhaant Sachin Thakker; Simranjeet Singh; Farhad Merchant; Vikas Rana; Anupam Chattopadhyay (VLSID, 2024)

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. - Lennart M. Reimann; Anschul Prashar; Chiara Ghinami; Rebecca Pelke; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (CoRR, 2024)

Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms. - Simranjeet Singh; Farhad Merchant; Sachin B. Patkar (CoRR, 2024)

IMPACT:InMemory ComPuting Architecture Based on Y-FlAsh Technology for Coalesced Tsetlin Machine Inference. - Omar Ghazal; Wei Wang; Shahar Kvatinsky; Farhad Merchant; Alex Yakovlev; Rishad A. Shafik (CoRR, 2024)

veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. - Chandan Kumar Jha 001; Khushboo Qayyum; Kemal Çaglar Coskun; Simranjeet Singh; Muhammad Hassan 002; Rainer Leupers; Farhad Merchant; Rolf Drechsler (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

ProMiSE: A Programmable Hardware Monitor for Secure Execution in Zero Trust Networks. - Nikhilesh Singh; Shagnik Pal; Rainer Leupers; Farhad Merchant; Chester Rebeiro (IEEE Embed. Syst. Lett., 2024)

Dependable Neuromorphic Computing-in-Memory Architectures. - Farhad Merchant; Ankit Bende; Markus Fritscher; Shahar Kvatinsky; Simranjeet Singh; Vikas Rana; Regina Dittmann; Keerthi Dorai Swamy Reddy; Christian Wenger; Fouwad Jamil Mir; Mottaqiallah Taouil; Manil Dev Gomony; et al. (ETS, 2025)