SystemCmantic: A high level Modelling and Co-Design Framework. - Lobna Kriaa; S. Adriano; Emmanuel Vaumorin; R. Nouacer; F. Blanc; S. Pajaniardja; Philippe Coussy; Eric Martin 001; Dominique Heller; Farhat Thabet; Anne-Marie Fouilliart (FDL, 2005)

Design Space Exploration of DSP Applications Based on Behavioral Description Models. - Farhat Thabet; Philippe Coussy; Dominique Heller; Eric Martin 001 (SiPS, 2006)

Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. - Farhat Thabet; Philippe Coussy; Dominique Heller; Eric Martin 001 (EUSIPCO, 2007)

Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. - Farhat Thabet; Philippe Coussy; Dominique Heller; Eric Martin 001 (J. Signal Process. Syst., 2009)

An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture. - Farhat Thabet; Yves Lhuillier; Caaliph Andriamisaina; Jean-Marc Philippe; Raphaël David (DATE, 2013)

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. - Edith Beigné; Ivan Miro-Panades; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Farhat Thabet; Benoît Tain; K. Benchehida; Sylvain Engels; Robin Wilson; et al. (ESSCIRC, 2013)

A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. - Ivan Miro Panades; Edith Beigné; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Anca Molnos; Farhat Thabet; Benoît Tain; Karim Ben Chehida; Sylvain Engels; et al. (IEEE J. Solid State Circuits, 2014)

HARS: A hardware-assisted runtime software for embedded many-core architectures. - Yves Lhuillier; Maroun Ojail; Alexandre Guerre; Jean-Marc Philippe; Karim Ben Chehida; Farhat Thabet; Caaliph Andriamisaina; Chafic Jaber; Raphaël David (ACM Trans. Embed. Comput. Syst., 2014)

Towards an Automatic Co-generator for Manycores' Architecture and Runtime: STHORM case-study. - Charly Bechara; Karim Ben Chehida; Farhat Thabet (ICCS, 2015)

Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs. - Samira Ait Bensaid; Mihail Asavoae; Farhat Thabet; Mathieu Jan (MEMOCODE, 2022)

Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code. - Samira Ait Bensaid; Mihail Asavoae; Farhat Thabet; Mathieu Jan (RTAS, 2022)