Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits. - Richard Burch; Farid N. Najm; Ping Yang 001; Dale E. Hocevar (DAC, 1988)

CREST-a current estimator for CMOS circuits. - Farid N. Najm; Richard Burch; Ping Yang 001; Ibrahim N. Hajj (ICCAD, 1988)

Computation of bus current variance for reliability estimation of VLSI circuits. - Farid N. Najm; Ibrahim N. Hajj; Ping Yang 001 (ICCAD, 1989)

Electromigration median time-to-failure based on a stochastic current waveform. - Farid N. Najm; Ibrahim N. Hajj; Ping Yang 001 (ICCD, 1989)

Probabilistic simulation for reliability analysis of VLSI circuits - Farid N. Najm (1989)

Probabilistic simulation for reliability analysis of CMOS VLSI circuits. - Farid N. Najm; Richard Burch; Ping Yang 001; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

The complexity of fault detection in MOS VLSI circuits. - Farid N. Najm; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Transition Density, A Stochastic Measure of Activity in Digital Circuits. - Farid N. Najm (DAC, 1991)

An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. - Farid N. Najm; Ibrahim N. Hajj; Ping Yang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Maximum Current Estimation in CMOS Circuits. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (DAC, 1992)

McPOWER: a Monte Carlo approach to power estimation. - Richard Burch; Farid N. Najm; Ping Yang 001; Timothy N. Trick (ICCAD, 1992)

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. - Harish Kriplani; Farid N. Najm; Ping Yang 001; Ibrahim N. Hajj (DAC, 1993)

Transition density: a new measure of activity in digital circuits. - Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A Monte Carlo approach for power estimation. - Richard Burch; Farid N. Najm; Ping Yang 001; Timothy N. Trick (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Statistical Estimation of the Switching Activity in Digital Circuits. - Michael G. Xakellis; Farid N. Najm (DAC, 1994)

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (ISCAS, 1994)

Low-pass filter for computing the transition density in digital circuits. - Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A survey of power estimation techniques in VLSI circuits. - Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits. - Farid N. Najm (DAC, 1995)

Power Estimation in Sequential Circuits. - Farid N. Najm; Shashank Goel; Ibrahim N. Hajj (DAC, 1995)

Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits. - Farid N. Najm; Michael Y. Zhang (DAC, 1995)

Power estimation techniques for integrated circuits. - Farid N. Najm (ICCAD, 1995)

Towards a high-level power estimation capability. - Farid N. Najm (ISLPD, 1995)

Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

High-level power estimation and the area complexity of Boolean functions. - Mahadevamurty Nemani; Farid N. Najm (ISLPED, 1996)

Towards a high-level power estimation capability [digital ICs]. - Mahadevamurty Nemani; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Power Macromodeling for High Level Power Estimation. - Subodh Gupta; Farid N. Najm (DAC, 1997)

Technology-Dependent Transformations for Low-Power Synthesis. - Rajendran Panda; Farid N. Najm (DAC, 1997)

Monte-Carlo approach for power estimation in sequential circuits. - Vikram Saxena; Farid N. Najm; Ibrahim N. Hajj (ED&TC, 1997)

Accurate power estimation for large sequential circuits. - Joseph N. Kozhaya; Farid N. Najm (ICCAD, 1997)

Delay Estimation VLSI Circuits from a High-Level View. - Mahadevamurty Nemani; Farid N. Najm (DAC, 1998)

Statistical Estimation of the , Switching Activity in VLSI Circuits. - Farid N. Najm; Michael G. Xakellis (VLSI Design, 1998)

Guest Editorial. - Farid N. Najm; Gary Yeap (VLSI Design, 1998)

Post-Mapping Transformations for Low-Power Synthesis. - Rajendran Panda; Farid N. Najm (VLSI Design, 1998)

Power macro-models for DSP blocks with application to high-level synthesis. - Subodh Gupta; Farid N. Najm (ISLPED, 1999)

Energy-per-cycle estimation at RTL. - Subodh Gupta; Farid N. Najm (ISLPED, 1999)

An optimization technique for dual-output domino logic. - Sumant Ramprasad; Ibrahim N. Hajj; Farid N. Najm (ISLPED, 1999)

High-level area and power estimation for VLSI circuits. - Mahadevamurty Nemani; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

High-level power estimation with interconnect effects. - Kavel M. Büyüksahin; Farid N. Najm (ISLPED, 2000)

A Statistical Model for Electromigration Failures. - Gilbert Yoh; Farid N. Najm (ISQED, 2000)

Pre-layout estimation of individual wire lengths. - Srinivas Bodapati; Farid N. Najm (SLIP, 2000)

Analytical models for RTL power estimation of combinational andsequential circuits. - Subodh Gupta; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Power modeling for high-level power estimation. - Subodh Gupta; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2000)

I/O buffer placement methodology for ASICs. - Joseph N. Kozhaya; Sani R. Nassif; Farid N. Najm (ICECS, 2001)

A gate-level timing model for SOI circuits. - Mehrdad Shahriari; Farid N. Najm (ICECS, 2001)

Frequency-domain supply current macro-model. - Srinivas Bodapati; Farid N. Najm (ISLPED, 2001)

Prelayout estimation of individual wire lengths. - Srinivas Bodapati; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Power estimation for large sequential circuits. - Joseph N. Kozhaya; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2001)

High-level current macro-model for power-grid analysis. - Srinivas Bodapati; Farid N. Najm (DAC, 2002)

Power-aware technology mapping for LUT-based FPGAs. - Jason Helge Anderson; Farid N. Najm (FPT, 2002)

High-level area estimation. - Kavel M. Büyüksahin; Farid N. Najm (ISLPED, 2002)

A multigrid-like technique for power grid analysis. - Joseph N. Kozhaya; Sani R. Nassif; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Estimation of state line statistics in sequential circuits. - Vikram Saxena; Farid N. Najm; Ibrahim N. Hajj (ACM Trans. Design Autom. Electr. Syst., 2002)

A technique for Improving dual-output domino logic. - Sumant Ramprasad; Ibrahim N. Hajj; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations. - Imad A. Ferzli; Farid N. Najm (DAC, 2003)

A static pattern-independent technique for power grid voltage integrity verification. - Dionysios Kouroussis; Farid N. Najm (DAC, 2003)

Timing Analysis in Presence of Power Supply and Ground Voltage Variations. - Rubil Ahmadi; Farid N. Najm (ICCAD, 2003)

Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations. - Imad A. Ferzli; Farid N. Najm (ICCAD, 2003)

ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. - Kavel M. Büyüksahin; Priyadarsan Patra; Farid N. Najm (ISLPED, 2003)

Design Techniques for Gate-Leakage Reduction in CMOS Circuits. - Rafik S. Guindi; Farid N. Najm (ISQED, 2003)

Switching activity analysis and pre-layout activity prediction for FPGAs. - Jason Helge Anderson; Farid N. Najm (SLIP, 2003)

Low-leakage asymmetric-cell SRAM. - Navid Azizi; Farid N. Najm; Andreas Moshovos (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Energy and peak-current per-cycle estimation at RTL. - Subodh Gupta; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Interconnect capacitance estimation for FPGAs. - Jason Helge Anderson; Farid N. Najm (ASP-DAC, 2004)

A novel low-power FPGA routing switch. - Jason Helge Anderson; Farid N. Najm (CICC, 2004)

Worst-case circuit delay taking into account power supply variations. - Dionysios Kouroussis; Rubil Ahmadi; Farid N. Najm (DAC, 2004)

Statistical timing analysis based on a timing yield model. - Farid N. Najm; Noel Menezes (DAC, 2004)

An analytical approach for dynamic range estimation. - Bin Wu; Jianwen Zhu; Farid N. Najm (DAC, 2004)

Active leakage power optimization for FPGAs. - Jason Helge Anderson; Farid N. Najm; Tim Tuan (FPGA, 2004)

Low-power programmable routing circuitry for FPGAs. - Jason Helge Anderson; Farid N. Najm (ICCAD, 2004)

Dynamic range estimation for nonlinear systems. - Bin Wu; Jianwen Zhu; Farid N. Najm (ICCAD, 2004)

An Asymmetric SRAM Cell to Lower Gate Leakage. - Navid Azizi; Farid N. Najm (ISQED, 2004)

Power estimation techniques for FPGAs. - Jason Helge Anderson; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Leakage power: trends, analysis and avoidance. - David T. Blaauw; Anirudh Devgan; Farid N. Najm (ASP-DAC, 2005)

Look-up table leakage reduction for FPGAs. - Navid Azizi; Farid N. Najm (CICC, 2005)

Variations-aware low-power design with voltage scaling. - Navid Azizi; Muhammad M. Khellah; Vivek De; Farid N. Najm (DAC, 2005)

On the need for statistical timing analysis. - Farid N. Najm (DAC, 2005)

A non-parametric approach for dynamic range estimation of nonlinear systems. - Bin Wu; Jianwen Zhu; Farid N. Najm (DAC, 2005)

Statistical timing analysis with two-sided constraints. - Khaled R. Heloue; Farid N. Najm (ICCAD, 2005)

Incremental partitioning-based vectorless power grid verification. - Dionysios Kouroussis; Imad A. Ferzli; Farid N. Najm (ICCAD, 2005)

Power grid voltage integrity verification. - Maha Nizam; Farid N. Najm; Anirudh Devgan (ISLPED, 2005)

Early power estimation for VLSI circuits. - Kavel M. Büyüksahin; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A Case for Asymmetric-Cell Cache Memories. - Andreas Moshovos; Babak Falsafi; Farid N. Najm; Navid Azizi (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme. - Kostas Pagiamtzis; Navid Azizi; Farid N. Najm (CICC, 2006)

A family of cells to reduce the soft-error-rate in ternary-CAM. - Navid Azizi; Farid N. Najm (DAC, 2006)

An adaptive FPGA architecture with process variation compensation and reduced leakage. - Georges Nabaa; Navid Azizi; Farid N. Najm (DAC, 2006)

Handling inductance in early power grid verification. - Nahi H. Abdul Ghani; Farid N. Najm (ICCAD, 2006)

Active leakage power optimization for FPGAs. - Jason Helge Anderson; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

High-level current macro model for logic blocks. - Srinivas Bodapati; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Analysis and verification of power grids considering process-induced leakage-current variations. - Imad A. Ferzli; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Voltage-Aware Static Timing Analysis. - Dionysios Kouroussis; Rubil Ahmadi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Dynamic-range estimation. - Bin Wu; Jianwen Zhu; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. - Khaled R. Heloue; Navid Azizi; Farid N. Najm (DAC, 2007)

Maximum circuit activity estimation using pseudo-boolean satisfiability. - Hratch Mangassarian; Andreas G. Veneris; Sean Safarpour; Farid N. Najm; Magdy S. Abadir (DATE, 2007)

A geometric approach for early power grid verification using current constraints. - Imad A. Ferzli; Farid N. Najm; Lars Kruse (ICCAD, 2007)

Early power grid verification under circuit current uncertainties. - Imad A. Ferzli; Farid N. Najm; Lars Kruse (ISLPED, 2007)

A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. - Farid N. Najm; Noel Menezes; Imad A. Ferzli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. - Navid Azizi; Muhammad M. Khellah; Vivek De; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Parameterized timing analysis with general delay models and arbitrary variation sources. - Khaled R. Heloue; Farid N. Najm (DAC, 2008)

Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. - Khaled R. Heloue; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. - Sari Onaissi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Fast vectorless power grid verification using an approximate inverse technique. - Nahi H. Abdul Ghani; Farid N. Najm (DAC, 2009)

Clock skew optimization via wiresizing for timing sign-off covering all process corners. - Sari Onaissi; Khaled R. Heloue; Farid N. Najm (DAC, 2009)

Quantifying robustness metrics in parameterized static timing analysis. - Khaled R. Heloue; Chandramouli V. Kashyap; Farid N. Najm (ICCAD, 2009)

PSTA-based branch and bound approach to the silicon speedpath isolation problem. - Sari Onaissi; Khaled R. Heloue; Farid N. Najm (ICCAD, 2009)

Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation. - Khaled R. Heloue; Navid Azizi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Low-Power Programmable FPGA Routing Circuitry. - Jason Helge Anderson; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Managing verification error traces with bounded model debugging. - Sean Safarpour; Andreas G. Veneris; Farid N. Najm (ASP-DAC, 2010)

Early P/G grid voltage integrity verification. - Mehmet Avci; Farid N. Najm (ICCAD, 2010)

Power grid correction using sensitivity analysis. - Meric Aydonat; Farid N. Najm (ICCAD, 2010)

Verification and Codesign of the Package and Die Power Delivery System Using Wavelets. - Imad A. Ferzli; Eli Chiprout; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Power grid verification using node and branch dominance. - Nahi H. Abdul Ghani; Farid N. Najm (DAC, 2011)

Power grid correction using sensitivity analysis under an RC model. - Pamela Al Haddad; Farid N. Najm (DAC, 2011)

A fast approach for static timing analysis covering all PVT corners. - Sari Onaissi; Feroze Taraporevala; Jinfeng Liu; Farid N. Najm (DAC, 2011)

Efficient RC power grid verification using node elimination. - Ankit Goyal; Farid N. Najm (DATE, 2011)

Fast Vectorless Power Grid Verification Under an RLC Model. - Nahi H. Abdul Ghani; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Incremental power grid verification. - Abhishek; Farid N. Najm (DAC, 2012)

Overview of vectorless/early power grid verification. - Farid N. Najm (ICCAD, 2012)

Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. - Khaled R. Heloue; Sari Onaissi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. - Hratch Mangassarian; Andreas G. Veneris; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Redundancy-aware electromigration checking for mesh power grids. - Sandeep Chatterjee; Mohammad Fawaz; Farid N. Najm (ICCAD, 2013)

A vectorless framework for power grid electromigration checking. - Mohammad Fawaz; Sandeep Chatterjee; Farid N. Najm (ICCAD, 2013)

Generating circuit current constraints to guarantee power grid safety. - Zahi Moudallal; Farid N. Najm (ASP-DAC, 2015)

Physical Design Challenges in the Chip Power Distribution Network. - Farid N. Najm (ISPD, 2015)

Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties. - Sandeep Chatterjee; Mohammad Fawaz; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Fast simulation-based verification of RC power grids. - Mohammad Fawaz; Farid N. Najm (CCECE, 2016)

Accurate verification of RC power grids. - Mohammad Fawaz; Farid N. Najm (DATE, 2016)

Fast physics-based electromigration checking for on-die power grids. - Sandeep Chatterjee; Valeriy Sukharev; Farid N. Najm (ICCAD, 2016)

A fast layer elimination approach for power grid reduction. - Abdul-Amir Yassine; Farid N. Najm (ICCAD, 2016)

Generating voltage drop aware current budgets for RC power grids. - Zahi Moudallal; Farid N. Najm (ISCAS, 2016)

Generating Current Budgets to Guarantee Power Grid Safety. - Zahi Moudallal; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Verification of the Power and Ground Grids Under General and Hierarchical Constraints. - Mehmet Avci; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems. - Sandeep Chatterjee; Valeriy Sukharev; Farid N. Najm (ICCAD, 2017)

Power grid verification under transient constraints. - Mohammad Fawaz; Farid N. Najm (ICCAD, 2017)

Power scheduling with active power grids. - Zahi Moudallal; Farid N. Najm (ICCAD, 2017)

Parallel Simulation-Based Verification of RC Power Grids. - Mohammad Fawaz; Farid N. Najm (ISVLSI, 2017)

Fast Vectorless RLC Grid Verification. - Mohammad Fawaz; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Generating Current Constraints to Guarantee RLC Power Grid Safety. - Zahi Moudallal; Farid N. Najm (ACM Trans. Design Autom. Electr. Syst., 2017)

Power Grid Electromigration Checking Using Physics-Based Models. - Sandeep Chatterjee; Valeriy Sukharev; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Power Grid Fixing for Electromigration-induced Voltage Failures. - Zahi Moudallal; Valeriy Sukharev; Farid N. Najm (ICCAD, 2019)

Efficient Simulation of Electromigration Damage in Large Chip Power Grids Using Accurate Physical Models (Invited Paper). - Farid N. Najm; Valeriy Sukharev (IRPS, 2019)

Power Scheduling With Active RC Power Grids. - Zahi Moudallal; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Electromigration Checking Using a Stochastic Effective Current Model. - Adam Issa; Valeriy Sukharev; Farid N. Najm (ICCAD, 2020)

Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids. - Valeriy Sukharev; Armen Kteyan; Farid N. Najm; Yong Hyeon Yi; Chris H. Kim; Jun-Ho Choy; Sofya Torosyan; Yu Zhu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution. - Armen Kteyan; Valeriy Sukharev; Alexander Volkov; Jun-Ho Choy; Farid N. Najm; Yong Hyeon Yi; Chris H. Kim; Stéphane Moreau (ISPD, 2023)

Fast Electromigration Simulation for Chip Power Grids. - Bijan Shahriari; Farid N. Najm (ISQED, 2023)

Fast Current Constraints Generation for Chip Safety. - Cedric Feghali; Farid N. Najm (ISQED, 2024)