An evaluation of a compiler optimization for improving the performance of a coherence directory. - Farnaz Mounes-Toussi; David J. Lilja; Zhiyuan Li 001 (International Conference on Supercomputing, 1994)

A Compiler-Assisted Scheme for Adaptive Cache Coherence Enforcement. - Trung N. Nguyen; Farnaz Mounes-Toussi; David J. Lilja; Zhiyuan Li 001 (IFIP PACT, 1994)

Write buffer design for cache-coherent shared-memory multiprocessors. - Farnaz Mounes-Toussi; David J. Lilja (ICCD, 1995)

The Potential of Compile-Time Analysis to Adapt the Cache Coherence Enforcement Strategy to the Data Sharing Characteristics. - Farnaz Mounes-Toussi; David J. Lilja (IEEE Trans. Parallel Distributed Syst., 1995)

The Effect of using State-Based Priority Information in a Shared-Memory Multiprocessor Cache Replacement Policy. - Farnaz Mounes-Toussi; David J. Lilja (ICPP, 1998)

SOI Implementation of a 64-Bit Adder. - J. V. Tran; Farnaz Mounes-Toussi; S. N. Storino; D. L. Stasiak (ICCD, 1999)

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology. - Daniel L. Stasiak; Farnaz Mounes-Toussi; Salvatore N. Storino (IEEE J. Solid State Circuits, 2001)

Hardware acceleration in the IBM PowerEN processor: architecture and performance. - Anil Krishna; Timothy Heil; Nicholas Lindberg; Farnaz Toussi; Steven VanderWiel (PACT, 2012)

Architecture and Performance of the Hardware Accelerators in IBM's PowerEN Processor. - Timothy Heil; Anil Krishna; Nicholas Lindberg; Farnaz Toussi; Steven VanderWiel (ACM Trans. Parallel Comput., 2014)

TraceRAR: An I/O Performance Evaluation Tool for Replaying, Analyzing, and Regenerating Traces. - Bingzhe Li; Farnaz Toussi; Clark Anderson; David J. Lilja; David H. C. Du (NAS, 2017)

NetStorage: A synchronized trace-driven replayer for network-storage system evaluation. - Bingzhe Li; Hao Wen 001; Farnaz Toussi; Clark Anderson; Bernard A. King-Smith; David J. Lilja; David H. C. Du (Perform. Evaluation, 2019)