A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm. - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li 001; Jayson Hu; Jong Park; et al. (ISSCC, 2008)

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS. - Cuong Trinh; Noboru Shibata; Takeshi Nakano; Mikio Ogawa; Jumpei Sato; Yoshikazu Takeyama; Katsuaki Isobe; Binh Le; Farookh Moogat; Nima Mokhlesi; Kenji Kozakai; Patrick Hong; et al. (ISSCC, 2009)

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology. - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li 001; Jayson Hu; Jonghak Yuh; et al. (IEEE J. Solid State Circuits, 2009)

128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode. - Yan Li; Seungpil Lee; Ken Oowada; Hao Nguyen; Qui Nguyen; Nima Mokhlesi; Cynthia Hsu; Jason Li 001; Venky Ramachandra; Teruhiko Kamei; Masaaki Higashitani; Tuan Pham; et al. (ISSCC, 2012)

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (ISSCC, 2012)

11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. - Ryuji Yamashita; Sagar Magia; Tsutomu Higuchi; Kazuhide Yoneya; Toshio Yamamura; Hiroyuki Mizukoshi; Shingo Zaitsu; Minoru Yamashita; Shunichi Toyama; Norihiro Kamae; Juan Lee; Shuo Chen; et al. (ISSCC, 2017)

A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface. - Jong Yuh; Jason Li 001; Heguang Li; Yoshihiro Oyama; Cynthia Hsu; Pradeep Anantula; Stanley Jeong; Anirudh Amarnath; Siddhesh Darne; Sneha Bhatia; Tianyu Tang; Aditya Arya; et al. (ISSCC, 2022)

A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface. - Jonghak Yuh; Yen-Lung Jason Li; Heguang Li; Yoshihiro Oyama; Cynthia Hsu; Pradeep Anantula; Gwang Yeong Stanley Jeong; Anirudh Amarnath; Siddhesh Darne; Sneha Bhatia; Tianyu Tang; Aditya Arya; et al. (IEEE J. Solid State Circuits, 2023)