Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown. - Barry J. O'Sullivan; Simon Van Beek; Philippe J. Roussel; Sidharth Rao; Wonsub Kim; Sebastien Couet; Johan Swerts; Farrukh Yasin; Dimitri Crotti; Dimitri Linten; Gouri Sankar Kar (IRPS, 2018)

SOT-MRAM 300mm integration for low power and ultrafast embedded memories. - Kevin Garello; Farrukh Yasin; Sebastien Couet; Laurent Souriau; Johan Swerts; Sidharth Rao; Simon Van Beek; Wonsub Kim; Enlong Liu; Shreya Kundu; Diana Tsvetanova; N. Jossart; et al. (CoRR, 2018)

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. - Trong Huynh Bao; Anabela Veloso; Sushil Sakhare; Philippe Matagne; Julien Ryckaert; Manu Perumkunnil; Davide Crotti; Farrukh Yasin; Alessio Spessot; Arnaud Furnémont; Gouri Sankar Kar; Anda Mocuta (DAC, 2019)

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. - Lizhou Wu; Siddharth Rao; Guilherme Cardoso Medeiros; Mottaqiallah Taouil; Erik Jan Marinissen; Farrukh Yasin; Sebastien Couet; Said Hamdioui; Gouri Sankar Kar (ETS, 2019)

Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM. - Kevin Garello; Farrukh Yasin; Hubert Hody; Sebastien Couet; Laurent Souriau; Shamin H. Sharifi; Johan Swerts; Robert Carpenter; Sidharth Rao; Wonsub Kim; J. Wu; K. K. V. Sethu; et al. (VLSI Circuits, 2019)

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. - Sidharth Rao; Woojin Kim; Simon Van Beek; Shreya Kundu; Manu Perumkunnil; Stefan Cosemans; Farrukh Yasin; Sebastien Couet; Robert Carpenter; Barry J. O'Sullivan; Shamin H. Sharifi; N. Jossart; et al. (IMW, 2021)

Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. - Simon Van Beek; Siddharth Rao; Shreya Kundu; Woojin Kim; Barry J. O'Sullivan; Stefan Cosemans; Farrukh Yasin; Robert Carpenter; Sebastien Couet; Shamin H. Sharifi; Nico Jossart; Davide Crotti; et al. (IRPS, 2021)

Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications. - Siddharth Rao; Kaiming Cai; Giacomo Talmelli; Nathali Franchina-Vergel; Ward Janssens; Hubert Hody; Farrukh Yasin; Kurt Wostyn; Sebastien Couet (IMW, 2023)

A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays. - W. Kim; Valerio Pica; N. Jossart; Farrukh Yasin; Kurt Wostyn; Sebastien Couet; Sidharth Rao (IMW, 2024)

Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. - Farrukh Yasin; A. Palomino; Ankit Kumar; Valerio Pica; Simon Van Beek; Giacomo Talmelli; Van D. Nguyen; Stefan Cosemans; D. Crotti; Kurt Wostyn; Gouri Sankar Kar; Sebastien Couet (VLSI Technology and Circuits, 2024)