Low-skew clock distribution using zero-phase-clock-buffer DLLs. - Ting Wu 003; Farshid Aryanfar; Haechang Lee; Jie Shen 010; T. J. Chin; Carl W. Werner; Ken Chang (ISSCC, 2010)

A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces. - Farshid Aryanfar; Amir Amirkhany (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels. - Shreyas Sen; Farshid Aryanfar; Carl W. Werner (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology. - Jing-Hwa Chen; S. R. Helmi; R. Azadegan; Farshid Aryanfar; S. Mohammadi (IEEE J. Solid State Circuits, 2013)

Millimeter-wave beamforming as an enabling technology for 5G cellular communications: theoretical feasibility and prototype results. - Wonil Roh; Ji-Yun Seol; Jeongho Park; Byunghwan Lee; Jaekon Lee; Yungsoo Kim; Jaeweon Cho; Kyungwhoon Cheun; Farshid Aryanfar (IEEE Commun. Mag., 2014)

A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators. - Mohammad Hekmat; Farshid Aryanfar; Jason Wei; Vijay P. Gadde; Reza Navid (IEEE J. Solid State Circuits, 2015)

A 28-GHz SiGe BiCMOS PA With 32% Efficiency and 23-dBm Output Power. - Anirban Sarkar; Farshid Aryanfar; Brian A. Floyd (IEEE J. Solid State Circuits, 2017)