Optimizing High Speed Flip-Flop Using Genetic Algorithm. - Fatemeh Aezinia; Ali Afzali-Kusha; Caro Lucas (APCCAS, 2006)

A Novel Low Power NOR gate in SOI CMOS Technology. - Fatemeh Aezinia; Behjat Forouzandeh (APCCAS, 2006)

Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops. - Fatemeh Aezinia; S. Najafzadeh; Ali Afzali-Kusha (APCCAS, 2006)

High performance circuit techniques for dynamic OR gates. - Bahman Kheradmand Boroujeni; Fatemeh Aezinia; Ali Afzali-Kusha (ISCAS, 2006)

Low power high performance level converter for dual supply voltage systems. - Fatemeh Aezinia; Ali Afzali-Kusha (IEICE Electron. Express, 2007)

Fine localization of photons on the pixellated detectors based on the analytical model. - Fatemeh Aezinia; S. Alireza Banani; Mani Malek Esmaeili (CCECE, 2010)

Three dimensional touchless tracking of objects using integrated capacitive sensors. - Fatemeh Aezinia; Yifan Wang; Behraad Bahreyni (IEEE Trans. Consumer Electron., 2012)

A low-power, low-cost switched-capacitor circuit for differential capacitive microsensors. - Fatemeh Aezinia; Behraad Bahreyni (CCECE, 2013)

A readout circuit with wide dynamic range for differential capacitive sensing applications. - Fatemeh Aezinia; Behraad Bahreyni (CCECE, 2013)

A low power CMOS integrated circuit for differential capacitive measurement. - Fatemeh Aezinia; Behraad Bahreyni (MWSCAS, 2013)

An Interface Circuit With Wide Dynamic Range for Differential Capacitive Sensing Applications. - Fatemeh Aezinia; Behraad Bahreyni (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Low-power, parasitic-insensitive interface circuit for capacitive microsensors. - Fatemeh Aezinia; Behraad Bahreyni (IET Circuits Devices Syst., 2016)