Application Specific Transistor Sizing for Low Power Full Adders. - Fatemeh Eslami; Amirali Baniasadi; Mostafa Farahani (ASAP, 2009)

A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic. - Tooraj Nikoubin; Fatemeh Eslami; Amirali Baniasadi; Keivan Navi (J. Low Power Electron., 2009)

Capacitive Boosting for FPGA Interconnection Networks. - Fatemeh Eslami; Mihai Sima (FPL, 2011)

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. - Eddie Hung; Fatemeh Eslami; Steven J. E. Wilton (FCCM, 2013)

Application Specific Low Leakage data Cache for embedded processors. - Mostafa Farahani; Fatemeh Eslami; Amirali Baniasadi (IGCC, 2013)

Incremental distributed trigger insertion for efficient FPGA debug. - Fatemeh Eslami; Steven J. E. Wilton (FPL, 2014)

An adaptive virtual overlay for fast trigger insertion for FPGA debug. - Fatemeh Eslami; Steven J. E. Wilton (FPT, 2015)

Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. - Fatemeh Eslami; Eddie Hung; Steven J. E. Wilton (CoRR, 2016)

An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. - Fatemeh Eslami; Steven J. E. Wilton (SIGARCH Comput. Archit. News, 2016)

Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. - Fatemeh Eslami; Eddie Hung; Steven J. E. Wilton (ETS, 2018)

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug. - Fatemeh Eslami; Steven J. E. Wilton (ACM Trans. Design Autom. Electr. Syst., 2018)