Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment. - M. H. Haghbayan; Sara Karamati; Fatemeh Javaheri; Zainalabedin Navabi (Asian Test Symposium, 2010)

Assertion based verification in TLM. - Amirali Ghofrani; Fatemeh Javaheri; Zainalabedin Navabi (EWDTS, 2010)

ESL design methodology for architecture exploration. - Fatemeh Javaheri; Zainalabedin Navabi (EWDTS, 2010)

Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization. - Amirali Ghofrani; Fatemeh Javaheri; Saeed Safari; Zainalabedin Navabi (SoC, 2010)

Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware. - Fatemeh Javaheri; Majid Namaki-Shoushtari; Parastoo Kamranfar; Zainalabedin Navabi (Asian Test Symposium, 2011)

BS 1149.1 extensions for an online interconnect fault detection and recovery. - Somayeh Sadeghi Kohan; Majid Namaki-Shoushtari; Fatemeh Javaheri; Zainalabedin Navabi (ITC, 2012)