A Split Method for Optimized Cost-Quality Hardware Implementation of Lifting-Based Discrete Wavelet Transform. - Alireza Aminlou; Fatemeh Refan; Maryam Homayouni; Omid Fatemi; Mahmoud Reza Hashemi (ICASSP (2), 2007)

Two Level Cost-Quality Optimization of 9-7 Lifting-Based Discrete Wavelet Transform. - Alireza Aminlou; Fatemeh Refan; Mahmoud Reza Hashemi; Omid Fatemi (ICIP (6), 2007)

An IEEE 1500 compatible wrapper architecture for testing cores at transaction level. - Fatemeh Refan; Paolo Prinetto; Zainalabedin Navabi (EWDTS, 2008)

Reliability in Application Specific Mesh-Based NoC Architectures. - Fatemeh Refan; Homa Alemzadeh; Saeed Safari; Paolo Prinetto; Zainalabedin Navabi (IOLTS, 2008)

"Plug & Test" at System Level via Testable TLM Primitives. - Homa Alemzadeh; Stefano Di Carlo; Fatemeh Refan; Paolo Prinetto; Zainalabedin Navabi (ITC, 2008)

A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages. - Alireza Aminlou; Fatemeh Refan; Mahmoud Reza Hashemi; Omid Fatemi; Saeed Safari (ICASSP, 2009)

NoC simulation modeling in DEVS-suite. - Hoda Ahmadinejad; Fatemeh Refan; Hessam S. Sarjoughian (SpringSim (TMS-DEVS), 2011)

Signature oriented model pruning to facilitate multi-threaded processors debugging. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (VTS, 2015)

Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2018)