Evaluation of FPGA routing architectures under process variation. - Fatemeh Sadat Pourhashemi; Morteza Saheb Zamani (ACM Great Lakes Symposium on VLSI, 2011)

Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only). - Fatemeh Sadat Pourhashemi; Morteza Saheb Zamani (FPGA, 2012)