Circuit-level techniques to control gate leakage for sub-100nm CMOS. - Fatih Hamzaoglu; Mircea R. Stan (ISLPED, 2002)

Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. - Fatih Hamzaoglu; Yibin Ye; Ali Keshavarzi; Kevin Zhang 001; Siva G. Narendra; Shekhar Borkar; Mircea R. Stan; Vivek De (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Non-Manhattan maze routing. - Mircea R. Stan; Fatih Hamzaoglu; David Garrett (SBCCI, 2004)

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2005)

A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. - Muhammad M. Khellah; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Yibin Ye; James W. Tschanz; Dinesh Somasekhar; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; Kevin Zhang 001; et al. (ISSCC, 2006)

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2006)

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; Ian Post; et al. (ISSCC, 2007)

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. - Muhammad M. Khellah; Dinesh Somasekhar; Yibin Ye; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Murad Sunna; James W. Tschanz; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; et al. (IEEE J. Solid State Circuits, 2007)

A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. - Fatih Hamzaoglu; Kevin Zhang 001; Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Yong-Gee Ng; Andrei Pavlov; Ken Smits; Mark Bohr (ISSCC, 2008)

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; et al. (IEEE J. Solid State Circuits, 2008)

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (ISSCC, 2009)

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. - Fatih Hamzaoglu; Kevin Zhang 001; Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Yong-Gee Ng; Andrei Pavlov; Ken Smits; Mark Bohr (IEEE J. Solid State Circuits, 2009)

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. - Muhammad M. Khellah; Nam-Sung Kim; Yibin Ye; Dinesh Somasekhar; Tanay Karnik; Nitin Borkar; Gunjan Pandya; Fatih Hamzaoglu; Tom Coan; Yih Wang; Kevin Zhang 001; Clair Webb; et al. (IEEE J. Solid State Circuits, 2009)

A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. - Hyunwoo Nho; Pramod Kolar; Fatih Hamzaoglu; Yih Wang; Eric Karl; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang 001 (ISSCC, 2010)

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. - Dinesh Somasekhar; Balaji Srinivasan; Gunjan Pandya; Fatih Hamzaoglu; Muhammad M. Khellah; Tanay Karnik; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2010)

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (IEEE J. Solid State Circuits, 2010)

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. - Fatih Hamzaoglu; Yih Wang; Pramod Kolar; Liqiong Wei; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE Des. Test Comput., 2011)

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. - Pramod Kolar; Eric Karl; Uddalak Bhattacharya; Fatih Hamzaoglu; Henry Nho; Yong-Gee Ng; Yih Wang; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2011)

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (ISSCC, 2012)

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Mesut Meterelliyoz; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (IEEE J. Solid State Circuits, 2013)

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. - Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang 001 (ISSCC, 2014)

2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology. - Mesut Meterelliyoz; Fuad H. Al-amoody; Umut Arslan; Fatih Hamzaoglu; Luke Hood; Manoj B. Lal; Jeffrey L. Miller; Anand Ramasundar; Dan Soltman; Ifar Wan; Yih Wang; Kevin Zhang 001 (VLSIC, 2014)

F2: Memory trends: From big data to wearable devices. - Jonathan Chang; Leland Chang; Antoine Dupret; Chulwoo Kim; Fatih Hamzaoglu; Takefumi Yoshikawa (ISSCC, 2015)

Session 7 overview: Non-volatile memory solutions: Memory subcommittee. - Fatih Hamzaoglu; Takashi Kono (ISSCC, 2015)

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. - Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2015)

An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS. - Avishek Biswas; Umut Arslan; Fatih Hamzaoglu; Anantha P. Chandrakasan (CICC, 2017)

Session 12 overview: SRAM. - Fatih Hamzaoglu; Chun Shiah; Leland Chang (ISSCC, 2017)

Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees. - Naveen Verma; Fatih Hamzaoglu; Makoto Nagata; Leland Chang (ISSCC, 2018)

eNVM MRAM Retention Reliability Modeling in 22FFL FinFET Technology. - James A. O'Donnell; Chris Connor; Tanmoy Pramanik; Jeff Hicks; Juan G. Alzate; Fatih Hamzaoglu; Justin Brockman; Oleg Golonzka; Kevin Fischer (IRPS, 2019)

A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V. - Pulkit Jain; Umut Arslan; Meenakshi Sekhar; Blake C. Lin; Liqiong Wei; Tanaya Sahu; Juan Alzate-vinasco; Ajay Vangapaty; Mesut Meterelliyoz; Nathan Strutt; Albert B. Chen; Patrick Hentges; et al. (ISSCC, 2019)

A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique. - Liqiong Wei; Juan G. Alzate; Umut Arslan; Justin Brockman; Nilanjan Das; Kevin Fischer; Tahir Ghani; Oleg Golonzka; Patrick Hentges; Rawshan Jahan; Pulkit Jain; Blake C. Lin; et al. (ISSCC, 2019)

Embedded Memories for Silicon-In-Package: Optimization of Memory Subsystem from IoT to Machine Learning. - Fatih Hamzaoglu (VLSI-DAT, 2019)

16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing. - Shanshan Xie; Can Ni; Aseem Sayal; Pulkit Jain; Fatih Hamzaoglu; Jaydeep P. Kulkarni (ISSCC, 2021)

Advances in Microprocessor Cache Architectures Over the Last 25 Years. - Ravi R. Iyer 001; Vivek De; Ramesh Illikkal; David A. Koufaty; Bhushan Chitlur; Andrew Herdrich; Muhammad M. Khellah; Fatih Hamzaoglu; Eric Karl (IEEE Micro, 2021)

Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs. - Shanshan Xie; Can Ni; Pulkit Jain; Fatih Hamzaoglu; Jaydeep P. Kulkarni (VLSI Technology and Circuits, 2022)

eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters. - Shanshan Xie; Can Ni; Aseem Sayal; Pulkit Jain; Fatih Hamzaoglu; Jaydeep P. Kulkarni (IEEE J. Solid State Circuits, 2024)