Xilinx FPGA implementation of an image classifier for object detection applications. - Peter McCurry; Fearghal Morgan; Liam Kilmartin (ICIP (3), 2001)

Applied VHDL training methodology, EDA framework and hardware implementation platform. - Fearghal Morgan; Patrick Rocke; Martin O'Halloran (ReConFig, 2005)

Platform for intrinsic evolution of analogue neural networks. - Patrick Rocke; John Maher; Fearghal Morgan (ReConFig, 2005)

Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices. - John Maher; Brian McGinley; Patrick Rocke; Fearghal Morgan (FCCM, 2006)

Transparent Management of Reconfigurable Hardware in Embedded Operating Systems. - Krzysztof Kosciuszkiewicz; Krzysztof Kepa; Fearghal Morgan (ISVLSI, 2006)

Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller. - Patrick Rocke; Brian McGinley; Fearghal Morgan; John Maher (ARC, 2007)

Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux. - Krzysztof Kosciuszkiewicz; Fearghal Morgan; Krzysztof Kepa (FPT, 2007)

SeReCon: A Trusted Environment for SoPC Design. - Krzysztof Kepa; Fearghal Morgan; Krzysztof Kosciuszkiewicz; Tomasz Surmacz (DepCoS-RELCOMEX, 2008)

Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. - Jim Harkin; Fearghal Morgan; Steve Hall; Piotr Dudek; Thomas Dowrick; Liam McDaid (FPL, 2008)

Maintaining diversity through adaptive selection, crossover and mutation. - Brian McGinley; Fearghal Morgan; Colm O'Riordan (GECCO, 2008)

Reconfigurable analogue hardware evolution of adaptive spiking neural network controllers. - Brian McGinley; Patrick Rocke; Fearghal Morgan; John Maher (GECCO, 2008)

Investigating the Suitability of FPAAs for Evolved Hardware Spiking Neural Networks. - Patrick Rocke; Brian McGinley; John Maher; Fearghal Morgan; Jim Harkin (ICES, 2008)

SeReCon: A Secure Dynamic Partial Reconfiguration Controller. - Krzysztof Kepa; Fearghal Morgan; Krzysztof Kosciuszkiewicz; Tomasz Surmacz (ISVLSI, 2008)

FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. - Krzysztof Kepa; Fearghal Morgan; Krzysztof Kosciuszkiewicz; Lars Braun; Michael Hübner 001; Jürgen Becker 001 (ARC, 2009)

Evolving plastic responses in artificial cell models. - John Maher; Fearghal Morgan; Oisin Mac Aodha (IEEE Congress on Evolutionary Computation, 2009)

IP protection in Partially Reconfigurable FPGAs. - Krzysztof Kepa; Fearghal Morgan; Krzysztof Kosciuszkiewicz (FPL, 2009)

A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks. - Jim Harkin; Fearghal Morgan; Liam McDaid; Steve Hall; Brian McGinley; Seamus Cawley (Int. J. Reconfigurable Comput., 2009)

An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations. - Snaider Carrillo; Jim Harkin; Liam McDaid; Sandeep Pande; Fearghal Morgan (ICES, 2010)

EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures. - Sandeep Pande; Fearghal Morgan; Seamus Cawley; Brian McGinley; Snaider Carrillo; Jim Harkin; Liam McDaid (SoC, 2010)

SeReCon: a secure reconfiguration controller for self-reconfigurable systems. - Krzysztof Kepa; Fearghal Morgan; Krzysztof Kosciuszkiewicz; Tomasz Surmacz (Int. J. Crit. Comput. Based Syst., 2010)

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. - Krzysztof Kepa; Fearghal Morgan; Krzysztof Kosciuszkiewicz; Lars Braun; Michael Hübner 001; Jürgen Becker 001 (ACM Trans. Reconfigurable Technol. Syst., 2010)

Guest Editorial ARC 2009. - Roger F. Woods; Jürgen Becker 001; Peter Athanas; Fearghal Morgan (ACM Trans. Reconfigurable Technol. Syst., 2010)

ERDB: An Embedded Routing Database for Reconfigurable Systems. - Krzysztof Kepa; Fearghal Morgan; Peter Athanas (FPL, 2011)

Remote FPGA Lab with Interactive Control and Visualisation Interface. - Fearghal Morgan; Seamus Cawley; Frank Callaly; Shane Agnew; Patrick Rocke; Martin O'Halloran; Nina Drozd; Krzysztof Kepa; Brian McGinley (FPL, 2011)

Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations. - Snaider Carrillo; Jim Harkin; Liam McDaid; Sandeep Pande; Seamus Cawley; Fearghal Morgan (ICANN (1), 2011)

Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures. - Sandeep Pande; Fearghal Morgan; Seamus Cawley; Brian McGinley; Jim Harkin; Snaider Carrillo; Liam McDaid (IJCCI (NCTA), 2011)

Enhancing learning of digital systems using a remote FPGA lab. - Fearghal Morgan; Seamus Cawley (ReCoSoC, 2011)

Hardware spiking neural network prototyping and application. - Seamus Cawley; Fearghal Morgan; Brian McGinley; Sandeep Pande; Liam McDaid; Snaider Carrillo; Jim Harkin (Genet. Program. Evolvable Mach., 2011)

Maintaining Healthy Population Diversity Using Adaptive Crossover, Mutation, and Selection. - Brian McGinley; John Maher; Colm O'Riordan; Fearghal Morgan (IEEE Trans. Evol. Comput., 2011)

Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. - Snaider Carrillo; Jim Harkin; L. J. McDaid; Sandeep Pande; Seamus Cawley; Brian McGinley; Fearghal Morgan (NOCS, 2012)

Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers. - Snaider Carrillo; Jim Harkin; Liam McDaid; Sandeep Pande; Seamus Cawley; Brian McGinley; Fearghal Morgan (Neural Networks, 2012)

Remote FPGA Lab for Enhancing Learning of Digital Systems. - Fearghal Morgan; Seamus Cawley; David Newell (ACM Trans. Reconfigurable Technol. Syst., 2012)

The Influence of Cell Type on Artificial Development. - John Maher; Fearghal Morgan; Colm O'Riordan; Brian McGinley (ECAL, 2013)

Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network. - Sandeep Pande; Fearghal Morgan; Seamus Cawley; Tom M. Bruintjes; Gerard J. M. Smit; Brian McGinley; Snaider Carrillo; Jim Harkin; Liam McDaid (Neural Process. Lett., 2013)

Fixed latency on-chip interconnect for hardware spiking neural network architectures. - Sandeep Pande; Fearghal Morgan; Gerard J. M. Smit; Tom M. Bruintjes; Jochem H. Rutgers; Brian McGinley; Seamus Cawley; Jim Harkin; Liam McDaid (Parallel Comput., 2013)

Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations. - Snaider Carrillo; Jim Harkin; Liam McDaid; Fearghal Morgan; Sandeep Pande; Seamus Cawley; Brian McGinley (IEEE Trans. Parallel Distributed Syst., 2013)

The Si elegans Project - The Challenges and Prospects of Emulating Caenorhabditis elegans. - Axel W. Blau; Frank Callaly; Seamus Cawley; Aedan Coffey; Alessandro De Mauro; Gorka Epelde; Lorenzo Ferrara; Finn Krewer; Carlo Liberale; Pedro Machado; Gregory Maclair; Thomas Martin McGinnity; et al. (Living Machines, 2014)

Exploring Neural Principles with Si elegans, a Neuromimetic Representation of the Nematode Caenorhabditis elegans. - Axel W. Blau; Frank Callaly; Seamus Cawley; Aedan Coffey; Alessandro De Mauro; Gorka Epelde; Lorenzo Ferrara; Finn Krewer; Carlo Liberale; Pedro Machado; Gregory Maclair; Thomas Martin McGinnity; et al. (NEUROTECHNIX, 2014)

Neuron Models in FPGA Hardware - A Route from High Level Descriptions to Hardware Implementations. - Finn Krewer; Aedan Coffey; Frank Callaly; Fearghal Morgan (NEUROTECHNIX, 2014)

Web-enabled Neuron Model Hardware Implementation and Testing. - Fearghal Morgan; Finn Krewer; Frank Callaly; Aedan Coffey; Brian Mc Ginley (NEUROTECHNIX, 2015)

Embedded Real-time Implementation of a Computational Efficient Optical Flow Extraction Method for Intelligent Robot Control Applications. - Robert Moni; László Bakó; Szabolcs Hajdú; Fearghal Morgan; Sándor-Tihamér Brassai (AICS, 2016)

Astrocyte to spiking neuron communication using Networks-on-Chip ring topology. - George Martin; Jim Harkin; Liam McDaid; John J. Wade; Junxiu Liu; Fearghal Morgan (SSCI, 2016)

Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors. - László Bakó; Szabolcs Hajdú; Fearghal Morgan (MACRo, 2017)

Rapid application prototyping for hardware modular spiking neural network architectures. - Sandeep Pande; Fearghal Morgan; Finn Krewer; Jim Harkin; Liam McDaid; Brian McGinley (Neural Comput. Appl., 2017)

viciLogic2.0 Online Learning and Prototyping Using PYNQ. - Fearghal Morgan; Declan O'Loughlin; Jeremy Audiger; Yohan Boyer; Frank Callaly (FPL, 2018)

Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC. - Fearghal Morgan; Declan O'Loughlin; Jeremy Audiger; Yohan Boyer; Niall Timlin-Canning; Krzysztof Kepa; Seamus Cawley; Ian Gallivan; László Bakó; Frank Callaly (RSP, 2018)

Web-Based Interfaces for Virtual C. elegans Neuron Model Definition, Network Configuration, Behavioral Experiment Definition and Experiment Results Visualization. - Gorka Epelde; Fearghal Morgan; Andoni Mujika; Frank Callaly; Peter Leskovský; Brian McGinley; Roberto Álvarez 001; Axel W. Blau; Finn Krewer (Frontiers Neuroinformatics, 2018)

RISC-V Online Tutor. - Fearghal Morgan; Arthur Beretta; Ian Gallivan; Joseph Clancy; Frédéric Rousseau 001; Roshan George; László Bakó; Frank Callaly (REV, 2021)

HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - Testbench and EDA Project Generation. - Fearghal Morgan; John Patrick Byrne; Abishek Bupathi; Roshan George; Muhammad Adnan Elahi; Frank Callaly; Sean Kelly; Declan O'Loughlin (RSP, 2023)