Federico A. Altolaguirre

According to our database, Federico A. Altolaguirre authored at least 4 papers between 2013 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

Active ESD protection for input transistors in a 40-nm CMOS process.

Federico A. Altolaguirre, Ming-Dou Ker

Proceedings of the VLSI Design, Automation and Test, 2015

2014

Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process.

Federico A. Altolaguirre, Ming-Dou Ker

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology.

Federico A. Altolaguirre, Ming-Dou Ker

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology.

Federico A. Altolaguirre, Ming-Dou Ker

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013