Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology. - Federico A. Altolaguirre; Ming-Dou Ker (ISCAS, 2013)

Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. - Federico A. Altolaguirre; Ming-Dou Ker (VLSI-DAT, 2013)

Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process. - Federico A. Altolaguirre; Ming-Dou Ker (MWSCAS, 2014)

Active ESD protection for input transistors in a 40-nm CMOS process. - Federico A. Altolaguirre; Ming-Dou Ker (VLSI-DAT, 2015)