Polynomial-time algorithm for on-chip scratchpad memory partitioning. - Federico Angiolini; Luca Benini; Alberto Caprara (CASES, 2003)

A post-compiler approach to scratchpad mapping of code. - Federico Angiolini; Francesco Menichelli; Alberto Ferrero; Luca Benini; Mauro Olivieri (CASES, 2004)

Analyzing On-Chip Communication in a MPSoC Environment. - Mirko Loghi; Federico Angiolini; Davide Bertozzi; Luca Benini; Roberto Zafalon (DATE, 2004)

A Network Traffic Generator Model for Fast Network-on-Chip Simulation. - Shankar Mahadevan; Federico Angiolini; Michael Storgaard; Rasmus Grøndahl Olsen; Jens Sparsø; Jan Madsen (DATE, 2005)

xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips. - Stergios Stergiou; Federico Angiolini; Salvatore Carta; Luigi Raffo; Davide Bertozzi; Giovanni De Micheli (DATE, 2005)

Networks on Chips: A Synthesis Perspective. - Federico Angiolini; Paolo Meloni; Luca Benini; Salvatore Carta; Luigi Raffo (PARCO, 2005)

Fault tolerance overhead in network-on-chip flow control schemes. - Antonio Pullini; Federico Angiolini; Davide Bertozzi; Luca Benini (SBCCI, 2005)

Simultaneous memory and bus partitioning for SoC architectures. - Suresh Srinivasan; Federico Angiolini; Martino Ruggiero; Luca Benini; Narayanan Vijaykrishnan (SoCC, 2005)

A Traffic Injection Methodology with Support for System-Level Synchronization. - Shankar Mahadevan; Federico Angiolini; Jens Sparsø; Luca Benini; Jan Madsen (VLSI-SoC, 2005)

An efficient profile-based algorithm for scratchpad memory partitioning. - Federico Angiolini; Luca Benini; Alberto Caprara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

An integrated open framework for heterogeneous MPSoC design space exploration. - Federico Angiolini; Jianjiang Ceng; Rainer Leupers; Federico Ferrari; Cesare Ferri; Luca Benini (DATE, 2006)

Contrasting a NoC and a traditional interconnect fabric with layout awareness. - Federico Angiolini; Paolo Meloni; Salvatore Carta; Luca Benini; Luigi Raffo (DATE, 2006)

Designing application-specific networks on chips with floorplan information. - Srinivasan Murali; Paolo Meloni; Federico Angiolini; David Atienza; Salvatore Carta; Luca Benini; Giovanni De Micheli; Luigi Raffo (ICCAD, 2006)

Reliability Support for On-Chip Memories Using Networks-on-Chip. - Federico Angiolini; David Atienza; Srinivasan Murali; Luca Benini; Giovanni De Micheli (ICCD, 2006)

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. - Srinivasan Murali; Rutuparna Tamhankar; Federico Angiolini; Antonio Pullini; David Atienza; Luca Benini; Giovanni De Micheli (SoC, 2006)

Area and Power Modeling Methodologies for Networks-on-Chip. - Paolo Meloni; Salvatore Carta; Roberto Argiolas; Luigi Raffo; Federico Angiolini (Nano-Net, 2006)

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. - Srinivasan Murali; Paolo Meloni; Federico Angiolini; David Atienza; Salvatore Carta; Luca Benini; Giovanni De Micheli; Luigi Raffo (VLSI-SoC, 2006)

Designing Routing and Message-Dependent Deadlock Free Networks on Chips. - Srinivasan Murali; Paolo Meloni; Federico Angiolini; David Atienza; Salvatore Carta; Luca Benini; Giovanni De Micheli; Luigi Raffo (VLSI-SoC (Selected Papers), 2006)

Interactive presentation: Improving the fault tolerance of nanometric PLA designs. - Federico Angiolini; M. Haykel Ben Jamaa; David Atienza; Luca Benini; Giovanni De Micheli (DATE, 2007)

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow. - Igor Loi; Federico Angiolini; Luca Benini (Nano-Net, 2007)

NoC Design and Implementation in 65nm Technology. - Antonio Pullini; Federico Angiolini; Paolo Meloni; David Atienza; Srinivasan Murali; Luigi Raffo; Giovanni De Micheli; Luca Benini (NOCS, 2007)

Bringing NoCs to 65 nm. - Antonio Pullini; Federico Angiolini; Srinivasan Murali; David Atienza; Giovanni De Micheli; Luca Benini (IEEE Micro, 2007)

A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. - Federico Angiolini; Paolo Meloni; Salvatore Carta; Luigi Raffo; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Timing-Error-Tolerant Network-on-Chip Design Methodology. - Rutuparna Tamhankar; Srinivasan Murali; Stergios Stergiou; Antonio Pullini; Federico Angiolini; Luca Benini; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Area and Power Modeling for Networks-on-Chip with Layout Awareness. - Paolo Meloni; Igor Loi; Federico Angiolini; Salvatore Carta; Massimo Barbaro; Luigi Raffo; Luca Benini (VLSI Design, 2007)

Developing Mesochronous Synchronizers to Enable 3D NoCs. - Igor Loi; Federico Angiolini; Luca Benini (DATE, 2008)

Exploring architectural solutions for energy optimisations in bus-based system-on-chip. - Suresh Srinivasan; Lin Li 002; Martino Ruggiero; Federico Angiolini; Narayanan Vijaykrishnan; Luca Benini (IET Comput. Digit. Tech., 2008)

Network-on-Chip design and synthesis outlook. - David Atienza; Federico Angiolini; Srinivasan Murali; Antonio Pullini; Luca Benini; Giovanni De Micheli (Integr., 2008)

A Reactive and Cycle-True IP Emulator for MPSoC Exploration. - Shankar Mahadevan; Federico Angiolini; Jens Sparsø; Luca Benini; Jan Madsen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. - Dragomir Milojevic; Trevor E. Carlson; Kris Croes; Riko Radojcic; Diana F. Ragett; Dirk Seynhaeve; Federico Angiolini; Geert Van der Plas; Paul Marchal (3DIC, 2009)

Synthesis of low-overhead configurable source routing tables for network interfaces. - Igor Loi; Federico Angiolini; Luca Benini (DATE, 2009)

A method for calculating hard QoS guarantees for Networks-on-Chip. - Dara Rahmati; Srinivasan Murali; Luca Benini; Federico Angiolini; Giovanni De Micheli; Hamid Sarbazi-Azad (ICCAD, 2009)

A floorplan-aware interactive tool flow for NoC design and synthesis. - Mohammad Reza Kakoee; Federico Angiolini; Srinivasan Murali; Antonio Pullini; Ciprian Seiculescu; Luca Benini (SoCC, 2009)

Exploring programming model-driven QoS support for NoC-based platforms. - Jaume Joven; Andrea Marongiu; Federico Angiolini; Luca Benini; Giovanni De Micheli (CODES+ISSS, 2010)

Networks on Chips: from research to products. - Giovanni De Micheli; Ciprian Seiculescu; Srinivasan Murali; Luca Benini; Federico Angiolini; Antonio Pullini (DAC, 2010)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. - Igor Loi; Federico Angiolini; Shinobu Fujita; Subhasish Mitra; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Quest for the ultimate network-on-chip: the NaNoC project. - Alessandro Strano; Davide Bertozzi; Federico Angiolini; Leonardo Di G. Gregorio; Frank Olaf Sem-Jacobsen; Vladimir Todorov; José Flich; José Silla; Tobias Bjerregaard (INA-OCMC@HiPEAC, 2012)

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores. - Jaume Joven; Andrea Marongiu; Federico Angiolini; Luca Benini; Giovanni De Micheli (Parallel Comput., 2013)

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip. - Dara Rahmati; Srinivasan Murali; Luca Benini; Federico Angiolini; Giovanni De Micheli; Hamid Sarbazi-Azad (IEEE Trans. Computers, 2013)

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs. - Jaume Joven; Akash Bagdia; Federico Angiolini; P. Strid; David Castells-Rufas; Eduard Fernandez-Alonso; Jordi Carrabina; Giovanni De Micheli (IEEE Trans. Ind. Informatics, 2013)

A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies. - Alberto Ghiribaldi; Hervé Tatenguem Fankem; Federico Angiolini; Mikkel Bystrup Stensgaard; Tobias Bjerregaard; Davide Bertozzi (ASP-DAC, 2014)

Tackling the bottleneck of delay tables in 3D ultrasound imaging. - Aya Ibrahim; Pascal Hager; Andrea Bartolini; Federico Angiolini; Marcel Arditi; Luca Benini; Giovanni De Micheli (DATE, 2015)

Demo: Efficient delay and apodization for on-FPGA 3D ultrasound. - Ahmet Caner Yuzuguler; William Andrew Simon; Aya Ibrahim; Federico Angiolini; Marcel Arditi; Jean-Philippe Thiran; Giovanni De Micheli (DASIP, 2016)

Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer. - William Andrew Simon; Ahmet Caner Yuzuguler; Aya Ibrahim; Federico Angiolini; Marcel Arditi; Jean-Philippe Thiran; Giovanni De Micheli (FPL, 2016)

Single-FPGA 3D ultrasound beamformer. - Ahmet Caner Yuzuguler; William Andrew Simon; Aya Ibrahim; Federico Angiolini; Marcel Arditi; Jean-Philippe Thiran; Giovanni De Micheli (FPL, 2016)

Raspberry Pi driven flow-injection system for electrochemical continuous monitoring platforms. - Bruno Donato; Francesca Stradolini; Abuduwaili Tuoheti; Federico Angiolini; Danilo Demarchi; Giovanni De Micheli; Sandro Carrara (BioCAS, 2017)

Inexpensive 1024-channel 3D telesonography system on FPGA. - Aya Ibrahim; Damien Doy; Claudio Loureiro; Eliéva Pignat; Federico Angiolini; Marcel Arditi; Jean-Philippe Thiran; Giovanni De Micheli (BioCAS, 2017)

Live demonstration: Inexpensive 1024-channel 3D telesonography system on FPGA. - Aya Ibrahim; Damien Doy; Claudio Loureiro; Eliéva Pignat; Federico Angiolini; Marcel Arditi; Jean-Philippe Thiran; Giovanni De Micheli (BioCAS, 2017)

Single-FPGA complete 3D and 2D medical ultrasound imager. - Aya Ibrahim; William Andrew Simon; Damien Doy; Eliéva Pignat; Federico Angiolini; Marcel Arditi; Jean-Philippe Thiran; Giovanni De Micheli (DASIP, 2017)

1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA. - Federico Angiolini; Aya Ibrahim; William Andrew Simon; Ahmet Caner Yuzuguler; Marcel Arditi; Jean-Philippe Thiran; Giovanni De Micheli (DATE, 2017)

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging. - Aya Ibrahim; Pascal A. Hager; Andrea Bartolini; Federico Angiolini; Marcel Arditi; Jean-Philippe Thiran; Luca Benini; Giovanni De Micheli (IEEE Trans. Biomed. Circuits Syst., 2017)

Safe and Efficient Deployment of Data-Parallelizable Applications on Many-Core Platforms: Theory and Practice. - Stefanos Skalistis; Federico Angiolini; Giovanni De Micheli; Alena Simalatsar (IEEE Des. Test, 2018)

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging. - Aya Ibrahim; Shuping Zhang; Federico Angiolini; Marcel Arditi; Shinji Kimura; Satoshi Goto; Jean-Philippe Thiran; Giovanni De Micheli (IEEE Trans. Biomed. Circuits Syst., 2018)