Use of lithography simulation for the calibration of equation-based design rule checks. - David Abercrombie; Fedor Pikus; Cosmin Cazan (DAC, 2009)

A framework for logic-aware layout analysis. - Patrick Gibson; Ziyang Lu; Fedor Pikus; Sridhar Srinivasan (ISQED, 2010)

Parametric Hierarchy Recovery in Layout Extracted Netlists. - John Lee 002; Puneet Gupta 001; Fedor Pikus (ISVLSI, 2012)