Fei Li

According to our database1, Fei Li authored at least 20 papers between 2001 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2011
A 65nm flash-based FPGA fabric optimized for low cost and power.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2007
Field Programmability of Supply Voltages for FPGA Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Device and Architecture Cooptimization for FPGA Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2005
Circuits and architectures for field programmable gate array with configurable supply voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Power modeling and characteristics of field programmable gate arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Scheduling of Soft Real-Time Systems for Context-Aware Applications.
Proceedings of the 2005 Design, 2005

Device and architecture co-optimization for FPGA power reduction.
Proceedings of the 42nd Design Automation Conference, 2005

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Vdd programmability to reduce FPGA interconnect power.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Low-power technology mapping for FPGA architectures with dual supply voltages.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

FPGA power reduction using configurable dual-Vdd.
Proceedings of the 41th Design Automation Conference, 2004

High-level area and power-up current estimation considering rich cell library.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
High Level Area and Current Estimation.
Proceedings of the Integrated Circuit and System Design, 2003

Microarchitecture level power and thermal simulation considering temperature dependent leakage model.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Architecture evaluation for power-efficient FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
Estimation of Maximum Power-Up Current.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

2001
Maximum current estimation considering power gating.
Proceedings of the 2001 International Symposium on Physical Design, 2001


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