Maximum current estimation considering power gating. - Fei Li 003; Lei He 001 (ISPD, 2001)

Estimation of Maximum Power-Up Current. - Fei Li 003; Lei He 001; Kewal K. Saluja (ASP-DAC/VLSI Design, 2002)

Architecture evaluation for power-efficient FPGAs. - Fei Li 003; Deming Chen; Lei He 001; Jason Cong (FPGA, 2003)

Microarchitecture level power and thermal simulation considering temperature dependent leakage model. - Weiping Liao; Fei Li 003; Lei He 001 (ISLPED, 2003)

High Level Area and Current Estimation. - Fei Li 003; Lei He 001; Joseph M. Basile; Rakesh J. Patel; Hema Ramamurthy (PATMOS, 2003)

High-level area and power-up current estimation considering rich cell library. - Fei Li 003; Lei He 001; Joseph M. Basile; Rakesh J. Patel; Hema Ramamurthy (ASP-DAC, 2004)

FPGA power reduction using configurable dual-Vdd. - Fei Li 003; Yan Lin 001; Lei He 001 (DAC, 2004)

Low-power technology mapping for FPGA architectures with dual supply voltages. - Deming Chen; Jason Cong; Fei Li 003; Lei He 001 (FPGA, 2004)

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. - Fei Li 003; Yan Lin 001; Lei He 001; Jason Cong (FPGA, 2004)

Vdd programmability to reduce FPGA interconnect power. - Fei Li 003; Yan Lin 001; Lei He 001 (ICCAD, 2004)

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. - Yan Lin 001; Fei Li 003; Lei He 001 (ASP-DAC, 2005)

Device and architecture co-optimization for FPGA power reduction. - Lerong Cheng; Phoebe Wong; Fei Li 003; Yan Lin 001; Lei He 001 (DAC, 2005)

Scheduling of Soft Real-Time Systems for Context-Aware Applications. - Jennifer L. Wong; Weiping Liao; Fei Li 003; Lei He 001; Miodrag Potkonjak (DATE, 2005)

Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. - Yan Lin 001; Fei Li 003; Lei He 001 (FPGA, 2005)

Power modeling and characteristics of field programmable gate arrays. - Fei Li 003; Yizhou Lin; Lei He 001; Deming Chen; Jason Cong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Circuits and architectures for field programmable gate array with configurable supply voltage. - Yan Lin 001; Fei Li 003; Lei He 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Device and Architecture Cooptimization for FPGA Power Reduction. - Lerong Cheng; Fei Li 003; Yan Lin 001; Phoebe Wong; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Field Programmability of Supply Voltages for FPGA Power Reduction. - Fei Li 003; Yan Lin 001; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. - Deming Chen; Jason Cong; Chen Dong 003; Lei He 001; Fei Li 003; Chi-Chen Peng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A 65nm flash-based FPGA fabric optimized for low cost and power. - Jonathan W. Greene; Sinan Kaptanoglu; Wenyi Feng; Volker Hecht; Joel Landry; Fei Li 003; Anton Krouglyanskiy; Mihai Morosan; Val Pevzner (FPGA, 2011)