Maximal Models of Assertion Graph in GSTE. - Guowu Yang; Jin Yang 006; Xiaoyu Song; Fei Xie 004 (TAMC, 2006)

Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation. - Yan Chen 001; Yujing He; Fei Xie 004; Jin Yang 006 (FMCAD, 2007)

Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation. - Yan Chen 001; Fei Xie 004; Jin Yang 006 (DAC, 2008)

Formal Verification for High-Assurance Behavioral Synthesis. - Sandip Ray; Kecheng Hao; Yan Chen 001; Fei Xie 004; Jin Yang 006 (ATVA, 2009)

Optimizing equivalence checking for behavioral synthesis. - Kecheng Hao; Fei Xie 004; Sandip Ray; Jin Yang 006 (DATE, 2010)

Equivalence checking for behaviorally synthesized pipelines. - Kecheng Hao; Sandip Ray; Fei Xie 004 (DAC, 2012)

Handling design and implementation optimizations in equivalence checking for behavioral synthesis. - Zhenkun Yang; Sandip Ray; Kecheng Hao; Fei Xie 004 (DAC, 2013)

Equivalence checking for compiler transformations in behavioral synthesis. - Zhenkun Yang; Kecheng Hao; Kai Cong; Sandip Ray; Fei Xie 004 (ICCD, 2013)

Scalable Certification Framework for Behavioral Synthesis Front-End. - Zhenkun Yang; Kecheng Hao; Kai Cong; Li Lei; Sandip Ray; Fei Xie 004 (DAC, 2014)

Equivalence checking for function pipelining in behavioral synthesis. - Kecheng Hao; Sandip Ray; Fei Xie 004 (DATE, 2014)

Mechanical Certification of Loop Pipelining Transformations: A Preview. - Disha Puri; Sandip Ray; Kecheng Hao; Fei Xie 004 (ITP, 2014)

Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis. - Disha Puri; Sandip Ray; Kecheng Hao; Fei Xie 004 (ACL2, 2014)

Validating scheduling transformation for behavioral synthesis. - Zhenkun Yang; Kecheng Hao; Kai Cong; Li Lei; Sandip Ray; Fei Xie 004 (DATE, 2016)

CRETE: A Versatile Binary-Level Concolic Testing Framework. - Bo Chen 008; Christopher Havlicek; Zhenkun Yang; Kai Cong; Raghudeep Kannavara; Fei Xie 004 (FASE, 2018)

End-to-End Concolic Testing for Hardware/Software Co-Validation. - Bo Chen 008; Kai Cong; Zhenkun Yang; Qin Wang; Jialu Wang; Li Lei; Fei Xie 004 (ICESS, 2019)

Hardware/Software Co-monitoring. - Li Lei; Kai Cong; Zhenkun Yang; Bo Chen 008; Fei Xie 004 (CoRR, 2019)

Concolic Execution of NMap Scripts for Honeyfarm Generation. - Zhe Li 014; Bo Chen 008; Wu-chang Feng; Fei Xie 004 (MTD@CCS, 2021)

An Equivalence Checking Framework for Agile Hardware Design. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Pasquale Cocchini; Jin Yang 006 (ASP-DAC, 2023)

An Automated Verification Framework for HalideIR-Based Compiler Transformations. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Jeremy Casas; Pasquale Cocchini; Jin Yang 006 (DATE, 2023)

A Systematic Translation Validation Framework for MLIR-Based Compilers. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Pasquale Cocchini; Jin Yang 006 (Int. J. Softw. Eng. Knowl. Eng., 2024)

Enhancing Translation Validation of Compiler Transformations with Large Language Models. - Yanzhao Wang; Fei Xie 004 (Int. J. Softw. Eng. Knowl. Eng., 2025)