Sensitivity analysis of periodically switched linear circuits using an adjoint network technique. - Fei Yuan 005; Ajoy Opal (ISCAS (5), 1999)

Distortion analysis of periodically switched nonlinear circuits. - Fei Yuan 005; Ajoy Opal (ISCAS (5), 1999)

A new initialization technique in designing and testing phases of asynchronous circuits. - Kaamran Raahemifar; Fei Yuan 005; Farahnaz A. Mohammadi (ICECS, 2001)

Efficient transient analysis of nonlinear circuits using Volterra series and piecewise constant interpolation. - Fei Yuan 005; Kaamran Raahemifar; Farahnaz A. Mohammadi (ISCAS (3), 2001)

An overview of design techniques for CMOS phase detectors. - Sameh Soliman; Fei Yuan 005; Kaamran Raahemifar (ISCAS (5), 2002)

Statistical analysis of switched linear networks. - Fei Yuan 005 (ISCAS (1), 2002)

An efficient transient analysis algorithm for mildly nonlinearcircuits. - Fei Yuan 005; Ajoy Opal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Low voltage, low power operational amplifier. - Shahab Ardalan; Kaamran Raahemifar; Fei Yuan 005 (ICECS, 2003)

Time domain response and sensitivity of periodically switched nonlinear circuits. - Quan Li; Fei Yuan 005 (ISCAS (4), 2003)

A new differential CMOS current pre-amplifier for optical communications. - Bendong Sun; Fei Yuan 005 (ISCAS (1), 2003)

Inductive peaking in wideband CMOS current amplifiers. - Bendong Sun; Fei Yuan 005; Ajoy Opal (ISCAS (4), 2004)

0.18µm CMOS 10-Gb/s Current-Mode Serial Link Transmitters. - Fei Yuan 005; Jean Jiang (IEICE Trans. Inf. Syst., 2005)

A 0.13µm CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity. - Minghai Li; Fei Yuan 005 (ACM Great Lakes Symposium on VLSI, 2006)

A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links. - Fei Yuan 005 (ACM Great Lakes Symposium on VLSI, 2006)

A new area-efficient 4-PAM 10 Gb/s CMOS serial link transmitter. - Fei Yuan 005; Minghai Li (ISCAS, 2006)

Low-voltage CMOS current-mode preamplifier: analysis and design. - Fei Yuan 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Current-Mode Phase-Locked Loops with Low Supply Voltage Sensitivity. - Dominic DiClemente; Fei Yuan 005 (ISCAS, 2007)

A New CMOS BPSK Modulator with Optimal Transaction Bandwidth Control. - Adrian Tang 002; Fei Yuan 005; Eddie Law (ISCAS, 2007)

CMOS gyrator-C active transformers. - Fei Yuan 005 (IET Circuits Devices Syst., 2007)

Current-Mode Phase-Locked Loops - A New Architecture. - Dominic DiClemente; Fei Yuan 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A New Current-Mode Incremental Signaling Scheme With Applications to Gb/s Parallel Links. - Tao Wang; Fei Yuan 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Inter-signal timing skew compensation of parallel links with voltage-mode incremental signaling. - An Hu; Fei Yuan 005 (ISCAS, 2008)

A new WiMAX sigma-delta modulator with constant-Q active inductors. - Adrian Tang 002; Fei Yuan 005; Eddie Law (ISCAS, 2008)

CMOS current-mode integrating receivers for Gbytes/s parallel links. - Fei Yuan 005; Tao Wang (Microelectron. J., 2008)

Current-Mode Phase-Locked Loops With CMOS Active Transformers. - Dominic DiClemente; Fei Yuan 005; Adrian Tang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A New CMOS Active Transformer QPSK Modulator With Optimal Bandwidth Control. - Adrian Tang 002; Fei Yuan 005; Eddie Law (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Wide Frequency Tuning Range Active-inductor Voltage-controlled Oscillator for Ultra Wideband Applications. - Dominic DiClemente; Fei Yuan 005 (ISCAS, 2009)

Remote Frequency Calibration of Passive Wireless Microsensors and Transponders using Injection-locked Phase-locked Loop. - Nima Soltani; Fei Yuan 005 (ISCAS, 2009)

Inter-signal timing skew compensation of parallel links with current-mode incremental signalling. - An Hu; Fei Yuan 005 (IET Circuits Devices Syst., 2009)

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification. - Yong Chen; Fei Yuan 005; Gul N. Khan (Microelectron. J., 2009)

Parallel links with current-mode incremental signaling and per-pin skew compensation. - An Hu; Fei Yuan 005 (Microelectron. J., 2009)

Intersignal Timing Skew Compensation of Parallel Links With Voltage-Mode Incremental Signaling. - An Hu; Fei Yuan 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A step-up transformer impedance transformation technique for efficient power harvesting of passive transponders. - Nima Soltani; Fei Yuan 005 (Microelectron. J., 2010)

Nonharmonic Injection-Locked Phase-Locked Loops With Applications in Remote Frequency Calibration of Passive Wireless Transponders. - Nima Soltani; Fei Yuan 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A High-Gain Power-Matching Technique for Efficient Radio-Frequency Power Harvest of Passive Wireless Microsystems. - Nima Soltani; Fei Yuan 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

XTEA encryption based novel RFID security protocol. - Jack Yu; Gul N. Khan; Fei Yuan 005 (CCECE, 2011)

XTEA Based Secure Authentication Protocol for RFID Systems. - Gul N. Khan; Jack Yu; Fei Yuan 005 (ICCCN, 2011)

A Study of the Lock Range of Injection-Locked CMOS Active-Inductor Oscillators Using a Linear Control System Approach. - Yushi Zhou; Fei Yuan 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Passive voltage level shifters for analog signaling. - Xiongliang Lai; Fei Yuan 005 (NEWCAS, 2012)

A frequency-domain study of lock range of harmonic oscillators with multiple injections. - Fei Yuan 005; Yushi Zhou (NEWCAS, 2012)

A Phasor-Domain Study of Lock Range of Harmonic Oscillators With Multiple Injections. - Fei Yuan 005; Yushi Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Hardware realization of GALS based cortical column systems. - Anita Tino; Gul N. Khan; Fei Yuan 005 (AHS, 2013)

Towards Hardware Realizations of Intelligent Systems: A Cortical Column Approach. - Anita Tino; Gul N. Khan; Fei Yuan 005 (ICPP, 2013)

Low-power programmable charge-domain sampler with embedded N-path bandpass filter for software-defined radio. - Yushi Zhou; Norm M. Filiol; Shaul Peker; Fei Yuan 005 (ISCAS, 2013)

Two-dimensional eye-opening monitor for serial links. - Alaa R. Al-Taee; Fei Yuan 005; Andy Gean Ye (MWSCAS, 2013)

Remote calibration of wireless power harvest. - Xiongliang Lai; Fei Yuan 005 (MWSCAS, 2013)

Passive voltage shifters for analogue signaling. - Xiongliang Lai; Fei Yuan 005 (IET Circuits Devices Syst., 2013)

Frequency-Domain Study of Lock Range of Non-Harmonic Oscillators With Multiple Multi-Tone Injections. - Fei Yuan 005; Yushi Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A new adaptive Decision Feedback Equalizer using hexagon eye-opening monitor for multi Gbps data links. - Alaa R. Al-Taee; Fei Yuan 005; Andy Gean Ye (ISCAS, 2014)

New 2-D Eye-Opening Monitor for Gb/s Serial Links. - Alaa R. Al-Taee; Fei Yuan 005; Andy Gean Ye; Saman Sadr (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Minimum jitter adaptive decision feedback equalizer for 4PAM serial links. - Alaa R. Al-Taee; Fei Yuan 005; Andy Gean Ye (ISCAS, 2015)

0.25-4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2015)

A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2015)

Study of injection-locked non-harmonic oscillators using Volterra series. - Yushi Zhou; Fei Yuan 005 (IET Circuits Devices Syst., 2015)

A Quadrature Charge-Domain Sampling Mixer With Embedded FIR, IIR, and N-Path Filters. - Yushi Zhou; Norman M. Filiol; Fei Yuan 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Time-mode techniques for fast-locking phase-locked loops. - Durand Jarrett-Amor; Young Jun Park 002; Fei Yuan 005 (ISCAS, 2016)

Time integrator for mixed-mode signal processing. - Young Jun Park 002; Durand Jarrett-Amor; Fei Yuan 005 (ISCAS, 2016)

Data transient insensitive phase-locked loops. - Durand Jarrett-Amor; Fei Yuan 005 (NEWCAS, 2016)

A phasor-domain study of injection-locking of harmonic oscillators with multiple injections. - Fei Yuan 005 (NEWCAS, 2016)

Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection. - Alaa R. Al-Taee; Fei Yuan 005; Andy Gean Ye (Circuits Syst. Signal Process., 2016)

Calibration Technique for Maximum Power Harvest of Passive Wireless Microsystems. - Xiongliang Lai; Fei Yuan 005 (Circuits Syst. Signal Process., 2016)

An adaptive edge decision feedback equalizer with 4PAM signalling. - Matthew Dolan; Fei Yuan 005 (MWSCAS, 2017)

Data-transition adaptive decision feedback equalizer for 2/4PAM serial links. - Yue Li; Fei Yuan 005 (MWSCAS, 2017)

Adaptive data-transition decision feedback equalizer for serial links. - Yue Li; Fei Yuan 005 (MWSCAS, 2017)

Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2017)

1-1 MASH ΔΣ time-to-digital converter with differential cascode time integrator. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2017)

All-digital ΔΣ TDC with differential bi-directional gated-delay-line time integrator. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2017)

Adaptive 4PAM decision feedback equalizer with reduced number of slicers. - Yushi Zhou; Fei Yuan 005 (MWSCAS, 2017)

Two-step pulse-shrinking time-to-digital converter. - Young Jun Park 002; Fei Yuan 005 (Microelectron. J., 2017)

A Comparative Study Of Injection Locked Frequency Divider Using Harmonic Mixer In Weak And Strong Inversion. - Yushi Zhou; Jared Mercier; Fei Yuan 005 (MWSCAS, 2018)

Data-Transition Decision Feedback Equalizer with S3-LMS Adaptation Algorithm. - Yue Li; Fei Yuan 005 (NEWCAS, 2018)

Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator. - Parth Parekh; Fei Yuan 005 (NEWCAS, 2018)

Multi-Swarm based NoC Configuration and Synthesis. - Muhammad Obaidullah; Gul N. Khan; Fei Yuan 005 (NORCAS, 2018)

Design techniques of all-digital arithmetic units for time-mode signal processing. - Fei Yuan 005 (IET Circuits Devices Syst., 2018)

All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator. - Young Jun Park 002; Parth Parekh; Fei Yuan 005 (Microelectron. J., 2018)

Digitally Interpolated Pre-Skewed Delay-Line Digital-to-Time Converter with Minimum Nonlinearity and Latency. - Daniel Junehee Lee; Fei Yuan 005; Gul N. Khan (MWSCAS, 2019)

A Pre-Skewed Bi-Directional Gated Delay Line Bang-Bang Frequency Detector with Applications in 10 Gbps Serial Link Frequency-Locking. - Yue Li; Fei Yuan 005 (MWSCAS, 2019)

A 500-MS/s 8.4-ps Double-Edge Successive Approximation TDC in 65 nm CMOS. - Rashed Siddiqui; Fei Yuan 005; Yushi Zhou (MWSCAS, 2019)

Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration. - Fei Yuan 005; Parth Parekh (MWSCAS, 2019)

All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator. - Fei Yuan 005; Parth Parekh (MWSCAS, 2019)

Data-Transition Decision Feedback Equalizer with Edge-Emphasis Taps and Raised References. - Yue Li; Fei Yuan 005 (NEWCAS, 2019)

Sign3-LMS data-transition decision feedback equaliser. - Yue Li; Fei Yuan 005 (IET Circuits Devices Syst., 2019)

Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability. - Parth Parekh; Fei Yuan 005; Yushi Zhou (MWSCAS, 2020)

All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line. - Parth Parekh; Fei Yuan 005; Yushi Zhou (MWSCAS, 2020)

All-digital power-efficient integrating frequency difference-to-digital converter for GHz frequency-locking. - Yue Li; Fei Yuan 005 (IET Circuits Devices Syst., 2020)

Time-based all-digital Δ Σ time-to-digital converter with pre-skewed bi-directional gated delay line time integrator. - Fei Yuan 005; Parth Parekh (IET Circuits Devices Syst., 2020)

Analysis and Design of an All-Digital ∆Σ TDC via Time-Mode Signal Processing. - Fei Yuan 005; Parth Parekh (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Successive Approximation Register TDC in Time-Mode Signal Processing. - Daniel Junehee Lee; Fei Yuan 005; Yushi Zhou (MWSCAS, 2021)

Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing. - Parth Parekh; Fei Yuan 005; Yushi Zhou (MWSCAS, 2021)

Bootstrapping Techniques for Energy-Efficient SAR ADCs : A State-of-the-Art Review. - Fei Yuan 005 (MWSCAS, 2021)

An 8-bit digital-to-time converter with pre-skewing and time interpolation. - Daniel Junehee Lee; Fei Yuan 005; Gul N. Khan; Yushi Zhou (IET Circuits Devices Syst., 2021)

Adaptive data-transition decision feedback equaliser with edge emphasis. - Yue Li; Fei Yuan 005 (IET Circuits Devices Syst., 2021)

All-digital successive approximation TDC in time-mode signal processing. - Daniel Junehee Lee; Fei Yuan 005; Yushi Zhou (Microelectron. J., 2021)

Performance Limits of Gated Delay Line Time Integrators. - Fei Yuan 005 (CCECE, 2022)

Metastability Correction Techniques for TSPC-DFF with Applications in Vernier TDC. - Fei Yuan 005 (ISCAS, 2022)

Bi-Directional Gated Ring Oscillator Time Integrator for Time-Based Mixed-Signal Processing. - Parth Parekh; Fei Yuan 005; Yushi Zhou (MWSCAS, 2022)

All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal Processing. - Parth Parekh; Fei Yuan 005; Yushi Zhou (NEWCAS, 2022)

Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. - Parth Parekh; Fei Yuan 005; Yushi Zhou (Microelectron. J., 2022)

Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters. - Parth Parekh; Fei Yuan 005; Yushi Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Metastability Error Correction for True Single-Phase Clock DFF With Applications in Vernier TDC. - Fei Yuan 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

All-Digital Time Integrator with Bi-Directional Gated Ring Oscillator / Shift Register. - Fei Yuan 005 (ISCAS, 2023)

A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC. - Daniel Junehee Lee; Fei Yuan 005; Yushi Zhou (MWSCAS, 2023)

A 3.97 µW 11.2b 500 kS/s Hybrid SAR ADC via Time-Mode Signal Processing. - Ian Perczak; Fei Yuan 005 (MWSCAS, 2023)

Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC. - Daniel Junehee Lee; Fei Yuan 005; Yushi Zhou (NEWCAS, 2023)

Gated Ring Oscillator Time Amplifier with Applications in Time Integration. - Fei Yuan 005 (NEWCAS, 2023)

Bi-Directional Gated Ring Oscillator Time Integrator. - Fei Yuan 005; Parth Parekh; Yushi Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Sub-Threshold Delay-Locked Loop with Piecewise Linearization and Time-Mode Proportional-Integral Locking. - Wenhao Wu; Fei Yuan 005; Yushi Zhou (APCCAS, 2024)

An 800 kS/s 1.83 fJ/conv. 12b ADC via Voltage Successive Approximation and Gated Cyclic Vernier Time Digitization. - Ian Perczak; Fei Yuan 005 (ISCAS, 2024)

Gated Ring Oscillator Time Amplifier with Pico-Second Sensitivity and Applications in All-Digital Variable-Gain Time Integrator. - Fei Yuan 005 (ISCAS, 2024)

A 0.6-V 108-nW 100-kHz Sub-Threshold Delay-Locked Loop with Digital Linearization for Low-Power SAR ADC. - Wenhao Wu; Fei Yuan 005; Yushi Zhou (MWSCAS, 2024)

A Comparative Study of Dynamic Comparators in Low-Voltage SAR ADC. - Fei Yuan 005 (MWSCAS, 2024)

Edge-Triggered Bi-Directional Gated Delay Line Up-Down Counters. - Fei Yuan 005 (MWSCAS, 2024)

Design Techniques for Sample-and-Hold with Bootstrapping in Low-Power SAR ADC. - Fei Yuan 005 (NewCAS, 2024)

Gated Delay Line Up-Down Counters for Mixed-Signal Processing. - Fei Yuan 005 (NewCAS, 2025)

Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC. - Wenhao Wu; Fei Yuan 005; Yushi Zhou (IEEE Open J. Circuits Syst., 2025)

A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC. - Fei Yuan 005 (IEEE Open J. Circuits Syst., 2025)