A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. - Zi Wang; Jinshan Yue; Chaojie He; Zhuoyu Dai; Feibin Xiang; Zhaori Cong; Yifan He 003; Xiaoyu Feng; Yongpan Liu (ISCAS, 2023)

A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing. - Zhuoyu Dai; Feibin Xiang; Chaojie He; Zi Wang; Woyu Zhang; Yi Li 049; Jinshan Yue; Dashan Shang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer. - Xiangqu Fu; Qirui Ren; Hao Wu 084; Feibin Xiang; Qing Luo; Jinshan Yue; Yong Chen 005; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. - Chaojie He; Zi Wang; Feibin Xiang; Zhuoyu Dai; Yifan He 003; Jinshan Yue; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices. - Zhuoyu Dai; Feibin Xiang; Xiangqu Fu; Yifan He 003; Wenyu Sun; Yongpan Liu; Guanhua Yang; Feng Zhang 014; Jinshan Yue; Ling Li 013 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)