Logic BIST Architecture for System-Level Test and Diagnosis. - Jun Qian; Xingang Wang; Qinfu Yang; Fei Zhuang; Junbo Jia; Xiangfeng Li; Yuan Zuo; Jayanth Mekkoth; Jinsong Liu; Hao-Jan Chao; Shianling Wu; Huafeng Yang; et al. (Asian Test Symposium, 2009)

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Lizhen Yu; Hiroshi Furukawa; Xiaoqing Wen; Wen-Ben Jone; Nur A. Touba; FeiFei Zhao; Jinsong Liu; Hao-Jan Chao; Fangfang Li; Zhigang Jiang (DFT, 2010)