A new method for high-sensitivity noise measurements. - Carmine Ciofi; Felice Crupi; Calogero Pace (IEEE Trans. Instrum. Meas., 2002)

Micro-prober for wafer-level low-noise measurements in MOS devices. - Carmine Ciofi; Felice Crupi; Calogero Pace; Graziella Scandurra (IEEE Trans. Instrum. Meas., 2003)

Very low-noise, high-accuracy programmable voltage reference. - Calogero Pace; Carmine Ciofi; Felice Crupi (IEEE Trans. Instrum. Meas., 2003)

Extraction of the trap distribution responsible for SILCs in MOS structures from the measurements and simulations of DC and noise properties. - A. Nannipieri; Giuseppe Iannaccone; Felice Crupi (Microelectron. Reliab., 2004)

How to enlarge the bandwidth without increasing the noise in OP-AMP-based transimpedance amplifier. - Carmine Ciofi; Felice Crupi; Calogero Pace; Graziella Scandurra (IEEE Trans. Instrum. Meas., 2006)

Enhanced sensitivity cross-correlation method for voltage noise measurements. - Felice Crupi; Gino Giusi; Carmine Ciofi; Calogero Pace (IEEE Trans. Instrum. Meas., 2006)

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics. - Paolo Magnone; Calogero Pace; Felice Crupi; Gino Giusi (Microelectron. Reliab., 2007)

Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks. - Paolo Srinivasan; Felice Crupi; Eddy Simoen; Paolo Magnone; Calogero Pace; Durga Misra; Cor Claeys (Microelectron. Reliab., 2007)

A New Circuit Topology for the Realization of Very Low-Noise Wide-Bandwidth Transimpedance Amplifier. - Carmine Ciofi; Felice Crupi; Calogero Pace; Graziella Scandurra; Maurizio Patane (IEEE Trans. Instrum. Meas., 2007)

Detection and Classification of Single-Electron Jumps in Si Nanocrystal Memories. - Calogero Pace; Gino Giusi; Felice Crupi; Salvatore Lombardo (IEEE Trans. Instrum. Meas., 2008)

Cross-correlation-based trans-impedance amplifier for current noise measurements. - Gino Giusi; Calogero Pace; Felice Crupi (Int. J. Circuit Theory Appl., 2009)

Full Model and Characterization of Noise in Operational Amplifier. - Gino Giusi; Felice Crupi; Calogero Pace; Paolo Magnone (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits. - Paolo Magnone; Felice Crupi; Massimo Alioto; Ben Kaczer (ISCAS, 2010)

Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (ISCAS, 2011)

A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference. - Luca Magnelli; Felice Crupi; Pasquale Corsonello; Calogero Pace; Giuseppe Iannaccone (IEEE J. Solid State Circuits, 2011)

Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements. - Paolo Magnone; Felice Crupi; Massimo Alioto; Ben Kaczer; Brice De Jaeger (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs. - Tommaso Romeo; Luigi Pantisano; Eddy Simoen; Raymond Krom; Mitsuhiro Togo; N. Horiguchi; Jérôme Mitard; Aaron Thean; Guido Groeseneken; Cor Claeys; Felice Crupi (ESSDERC, 2012)

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. - Jacopo Franco; Ben Kaczer; Jérôme Mitard; Maria Toledano-Luque; Felice Crupi; Geert Eneman; Ph. J. Rousse; Tibor Grasser; M. Cho; Thomas Kauerauf; Liesbeth Witters; Geert Hellings; et al. (ICICDT, 2012)

BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic. - Jacopo Franco; S. Graziano; Ben Kaczer; Felice Crupi; Lars-Åke Ragnarsson; Tibor Grasser; Guido Groeseneken (Microelectron. Reliab., 2012)

A methodology to account for the finger interruptions in solar cell performance. - Raffaele De Rose; Antonio Malomo; Paolo Magnone; Felice Crupi; Giorgio Cellere; Marco Martire; Diego Tonini; Enrico Sangiorgi (Microelectron. Reliab., 2012)

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Mitsuhiro Togo; N. Horiguchi; Guido Groeseneken (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. - Marc Aoulaiche; Eddy Simoen; Romain Ritzenthaler; Tom Schram; Hiroaki Arimura; Moonju Cho; Thomas Kauerauf; Guido Groeseneken; Naoto Horiguchi; Aaron Thean; Antonio Federico; Felice Crupi; et al. (ESSDERC, 2013)

Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires. - Sebastiano Strangio; Pierpaolo Palestri; David Esseni; Luca Selmi; Felice Crupi (ESSDERC, 2014)

A picopower temperature-compensated, subthreshold CMOS voltage reference. - Domenico Albano; Felice Crupi; Francesca Cucchi; Giuseppe Iannaccone (Int. J. Circuit Theory Appl., 2014)

Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier. - Luca Magnelli; Francesco A. Amoroso; Felice Crupi; Gregorio Cappuccino; Giuseppe Iannaccone (Int. J. Circuit Theory Appl., 2014)

Origins and implications of increased channel hot carrier variability in nFinFETs. - Ben Kaczer; Jacopo Franco; M. Cho; Tibor Grasser; Philippe J. Roussel; Stanislav Tyaginov; M. Bina; Yannick Wimmer; Luis-Miguel Procel; Lionel Trojman; Felice Crupi; Gregory Pitner; et al. (IRPS, 2015)

Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. - Domenico Albano; Marco Lanuzza; Ramiro Taco; Felice Crupi (Int. J. Circuit Theory Appl., 2015)

A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity. - Luca Magnelli; Felice Crupi; Pasquale Corsonello; Giuseppe Iannaccone (Int. J. Circuit Theory Appl., 2015)

A Sub-kT/q Voltage Reference Operating at 150 mV. - Domenico Albano; Felice Crupi; Francesca Cucchi; Giuseppe Iannaccone (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design of a sub-1-V nanopower CMOS current reference. - Raffaele De Rose; Domenico Albano; Felice Crupi; Marco Lanuzza (ECCTD, 2017)

A variation-aware simulation framework for hybrid CMOS/spintronic circuits. - Raffaele De Rose; Marco Lanuzza; Felice Crupi; Giulio Siracusano; Riccardo Tomasello; Giovanni Finocchio; Mario Carpentieri; Massimo Alioto (ISCAS, 2017)

Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. - Raffaele De Rose; Greta Carangelo; Marco Lanuzza; Felice Crupi; Giovanni Finocchio; Mario Carpentieri (SMACD, 2017)

Low energy/delay overhead level shifter for wide-range voltage conversion. - Marco Lanuzza; Felice Crupi; Sandro Rao; Raffaele De Rose; Giuseppe Iannaccone (Int. J. Circuit Theory Appl., 2017)

A physical unclonable function based on a 2-transistor subthreshold voltage divider. - Raffaele De Rose; Felice Crupi; Marco Lanuzza; Domenico Albano (Int. J. Circuit Theory Appl., 2017)

An Ultralow-Voltage Energy-Efficient Level Shifter. - Marco Lanuzza; Felice Crupi; Sandro Rao; Raffaele De Rose; Sebastiano Strangio; Giuseppe Iannaccone (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Design of a 3T current reference for low-voltage, low-power operation. - Raffaele De Rose; Felice Crupi; Maksym Paliy; Marco Lanuzza; Giuseppe Iannaccone (ICICDT, 2018)

Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations. - Noemi Guerra; Raffaele De Rose; Marco Guevara; Paul Procel; Marco Lanuzza; Felice Crupi (RTSI, 2018)

A portable class of 3-transistor current references with low-power sub-0.5 V operation. - Felice Crupi; Raffaele De Rose; Maksym Paliy; Marco Lanuzza; Mattia Perna; Giuseppe Iannaccone (Int. J. Circuit Theory Appl., 2018)

A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. - Raffaele De Rose; Marco Lanuzza; Felice Crupi; Giulio Siracusano; Riccardo Tomasello; Giovanni Finocchio; Mario Carpentieri; Massimo Alioto (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. - Marco Lanuzza; Raffaele De Rose; Esteban Garzón; Felice Crupi (ASICON, 2019)

Characterization and Modeling of BTI in SiC MOSFETs. - Davide Cornigli; Andrea Natale Tallarico; Susanna Reggiani; Claudio Fiegna; Enrico Sangiorgi; Luis Sanchez; Carlos Valdivieso; Giuseppe Consentino; Felice Crupi (ESSDERC, 2019)

Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Marco Lanuzza (ICECS, 2019)

An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. - Marco Lanuzza; Raffaele De Rose; Felice Crupi; Massimo Alioto (ICECS, 2019)

Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions. - Carmelo Felicetti; Angelo Furfaro; Domenico Saccà; Massimo Vatalaro; Marco Lanuzza; Felice Crupi (IDCS, 2019)

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Giovanni Finocchio; Mario Carpentieri; Marco Lanuzza (SMACD, 2019)

A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (VLSI Circuits, 2020)

Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Giovanni Finocchio; Mario Carpentieri; Marco Lanuzza (Integr., 2020)

A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (ESSCIRC, 2021)

Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC. - Carmelo Felicetti; Marco Lanuzza; Antonino Rullo; Domenico Saccà; Felice Crupi (SmartIoT, 2021)

Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (IEEE J. Solid State Circuits, 2021)

A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter. - Luigi Fassio; Francesco Settino; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider. - Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi (ICECS 2022, 2022)

Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks. - Tatiana Moposita; Lionel Trojman; Felice Crupi; Marco Lanuzza; Andrei Vladimirescu (LASCAS, 2022)

Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Adam Teman; Marco Lanuzza (CoRR, 2022)

Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. - Raffaele De Rose; Tommaso Zanotti; Francesco Maria Puglisi; Felice Crupi; Paolo Pavan; Marco Lanuzza (CoRR, 2022)

Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. - Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi (IEEE J. Solid State Circuits, 2022)

Modified FMCW Scheme for Improved Ultrasonic Positioning and Ranging of Unmanned Ground Vehicles at Distances < 50 mm. - Stefano Laureti; Marco Mercuri; David Hutchins; Felice Crupi; Marco Ricci 001 (Sensors, 2022)

Analysis of Signal Processing Methods to Reject the DC Offset Contribution of Static Reflectors in FMCW Radar-Based Vital Signs Monitoring. - Marco Mercuri; Tom Torfs; Maxim Rykunov; Stefano Laureti; Marco Ricci 001; Felice Crupi (Sensors, 2022)

A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS. - Benjamin Zambrano; Esteban Garzón; Sebastiano Strangio; Felice Crupi; Marco Lanuzza (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

OSA evaluation by using clinical parameters monitoring system based on Radar Technology. - Marco Mercuri; Patrizia Vizza; Pierangelo Veltri; Felice Crupi (EWSN, 2023)

Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (IEEE Access, 2023)

SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. - Tatiana Moposita; Esteban Garzón; Raffaele De Rose; Felice Crupi; Andrei Vladimirescu; Lionel Trojman; Marco Lanuzza (IEEE Access, 2023)

Experimental analysis of variability in WS2-based devices for hardware security. - Massimo Vatalaro; H. Neill; F. Gity; Paolo Magnone; Vincenzo Maccaronio; C. Márquez; J. C. Galdon; F. Gamiz; Felice Crupi; P. Hurley; Raffaele De Rose (CoRR, 2023)

Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing. - Tatiana Moposita; Esteban Garzón; Felice Crupi; Lionel Trojman; Andrei Vladimirescu; Marco Lanuzza (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. - Fanny Spagnolo; Stefania Perri; Massimo Vatalaro; Fabio Frustaci; Felice Crupi; Pasquale Corsonello (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Design of a Temperature-Aware Voltage Generator for 2-Bit Read Operation in STT-MRAM Based SIMPLY Architecture. - Massimo Vatalaro; Vincenzo Maccaronio; Tommaso Zanotti; Erika Borellini; Felice Crupi; Francesco Maria Puglisi; Raffaele De Rose (ICICDT, 2025)

A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider. - Massimo Vatalaro; Raffaele De Rose; Vincenzo Maccaronio; Marco Lanuzza; Felice Crupi (ISCAS, 2025)

PUF-Based Authentication-Oriented Architecture for Identification Tags. - Antonino Rullo; Carmelo Felicetti; Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Domenico Saccà (IEEE Trans. Dependable Secur. Comput., 2025)

C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs. - Fanny Spagnolo; Massimo Vatalaro; Stefania Perri; Felice Crupi; Pasquale Corsonello (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations. - Massimo Vatalaro; Raffaele De Rose; Vincenzo Maccaronio; Marco Lanuzza; Felice Crupi (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)