Comparing Transistor-Level Implementations of 4-Input Logic Functions. - Felipe Ribeiro Schneider; Vinícius P. Correia; Renato P. Ribas; André Inácio Reis (IWLS, 2002)

Automatic Generation of Digital Cell Libraries. - João Daniel Togni; Felipe Ribeiro Schneider; Vinícius P. Correia; Renato P. Ribas; André Inácio Reis (SBCCI, 2002)

Unified Theory to Build Cell-Level Transistor Networks from BDDs. - Renato E. B. Poli; Felipe Ribeiro Schneider; Renato P. Ribas; André Inácio Reis (SBCCI, 2003)

Exact lower bound for the number of switches in series to implement a combinational logic cell. - Felipe Ribeiro Schneider; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (ICCD, 2005)

KARMA: A Didactic Tool for Two-Level Logic Synthesis. - Carlos Eduardo Klock; Felipe Ribeiro Schneider; M. V. N. Gomes; Dionatan S. Moura; Renato P. Ribas; André Inácio Reis (MSE, 2007)

A comparative study of CMOS gates with minimum transistor stacks. - Leomar S. da Rosa Jr.; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Felipe Ribeiro Schneider (SBCCI, 2007)

Switch level optimization of digital CMOS gate networks. - Leomar S. da Rosa Jr.; Felipe Ribeiro Schneider; Renato P. Ribas; André Inácio Reis (ISQED, 2009)