Testability Properties of BDDs. - Felipe S. Marques 001; Vinícius P. Correia; A. Prado; Marcelo Lubaszewski; André Inácio Reis (SBCCI, 2002)

Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy. - Renato Fernandes Hentschke; Felipe S. Marques 001; Fernanda Lima 001; Luigi Carro; Altamiro Amadeu Susin; Ricardo Reis 001 (SBCCI, 2002)

A new approach to the use of satisfiability in false path detection. - Felipe S. Marques 001; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2005)

Fast disjoint transistor networks from BDDs. - Leomar S. da Rosa Jr.; Felipe S. Marques 001; Tiago Muller Gil Cardoso; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (SBCCI, 2006)

DAG based library-free technology mapping. - Felipe S. Marques 001; Leomar S. da Rosa Jr.; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2007)

A comparative study of CMOS gates with minimum transistor stacks. - Leomar S. da Rosa Jr.; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Felipe Ribeiro Schneider (SBCCI, 2007)

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. - Tiago Muller Gil Cardoso; Leomar S. da Rosa Jr.; Felipe de Souza Marques; Renato P. Ribas; André Inácio Reis (ISQED, 2008)

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. - Osvaldo Martinello; Felipe S. Marques 001; Renato P. Ribas; André Inácio Reis (DATE, 2010)

SwitchCraft: a framework for transistor network design. - Vinicius Callegaro; Felipe de Souza Marques; Carlos Eduardo Klock; Leomar Soares da Rosa Jr.; Renato P. Ribas; André Inácio Reis (SBCCI, 2010)

Improvements on the detection of false paths by using unateness and satisfiability. - Felipe S. Marques 001; Osvaldo Martinello; Renato P. Ribas; André Inácio Reis (SBCCI, 2010)

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (SBCCI, 2012)

Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform. - Andrws Vieira; Daniel Debastiani; Luciano Volcan Agostini; Felipe S. Marques 001; Júlio C. B. de Mattos (SBESC, 2012)

Efficient transistor-level design of CMOS gates. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (ACM Great Lakes Symposium on VLSI, 2013)

Transistor-level optimization of CMOS complex gates. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (LASCAS, 2013)

Improving the methodology to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (SBCCI, 2013)

A new general purpose line probe routing algorithm. - Stephano Machado Moreira Goncalves; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (ICECS, 2014)

Exploring Independent Gates in FinFET-Based Transistor Network Generation. - Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar Soares da Rosa Jr. (SBCCI, 2014)

Evaluating Geometric Aspects of Non-Series-Parallel Cells. - Maicon Schneider Cardoso; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (SBCCI, 2015)

Topological characteristics of logic networks generated by a graph-based methodology. - Maicon Schneider Cardoso; Regis Zanandrea; Renato Souza de Souza; Joao Junior da Silva Machado; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (LASCAS, 2016)

Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. - Gustavo H. Smaniotto; Joao Junior da Silva Machado; Matheus T. Moreira; Adriel Mota Ziesemer; Felipe S. Marques 001; Leomar S. da Rosa Jr. (LASCAS, 2016)

Physical design of supergate cells aiming geometrical optimizations. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Regis Zanandrea; Renato Souza de Souza; Leomar S. da Rosa; Felipe de Souza Marques (MWSCAS, 2016)

Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. - Gustavo H. Smaniotto; Matheus T. Moreira; Adriel Mota Ziesemer; Felipe S. Marques 001; Leomar S. da Rosa (MWSCAS, 2016)

Graph-Based Transistor Network Generation Method for Supergate Design. - Vinicius Neves Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A post-processing methodology to improve the automatic design of CMOS gates at layout-level. - Gustavo H. Smaniotto; Regis Zanandrea; Maicon Schneider Cardoso; Renato Souza de Souza; Matheus T. Moreira; Felipe S. Marques 001; Leomar S. da Rosa Jr. (ICECS, 2017)

A survey of path search algorithms for VLSI detailed routing. - Stephano Machado Moreira Goncalves; Leomar S. da Rosa Jr.; Felipe de Souza Marques (ISCAS, 2017)

Post-processing of supergate networks aiming cell layout optimization. - Gustavo H. Smaniotto; Regis Zanandrea; Maicon Schneider Cardoso; Renato Souza de Souza; Matheus T. Moreira; Felipe S. Marques 001; Leomar S. da Rosa Jr. (ISCAS, 2017)

Simulated Annealing Applied to LUT-Based FPGA Technology Mapping. - Matheus Nachtigall; Paulo Ferreira; Felipe S. Marques 001 (MICAI (Special Session), 2017)

Transistor placement strategies for non-series-parallel cells. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Joao Junior da Silva Machado; Matheus T. Moreira; Leomar S. da Rosa; Felipe de Souza Marques (MWSCAS, 2017)

Transistor Count Optimization in IG FinFET Network Design. - Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

A Novel Sizing Method Aiming Security Against Differential Power Analysis. - Vitor G. Lima; Plinio Finkenauer; Vinícius V. Camargo; Felipe S. Marques 001; Leomar R. Junior; Rafael Iankowski Soares (ICECS, 2018)

Area-Aware Design of Static CMOS Complex Gates. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Andrei A. O. Bubolz; Leomar S. da Rosa Jr.; Felipe S. Marques 001 (NEWCAS, 2018)

A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing. - Stéphano M. M. Gonçalves; Leomar S. da Rosa; Felipe S. de Marques 001 (NEWCAS, 2018)

Libra: An Automatic Design Methodology for CMOS Complex Gates. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Andrei A. O. Bubolz; Matheus T. Moreira; Leomar S. da Rosa Jr.; Felipe de Souza Marques (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An Improved Heuristic Function for A∗-Based Path Search in Detailed Routing. - Stéphano M. M. Gonçalves; Leomar S. da Rosa; Felipe S. de Marques 001 (ISCAS, 2019)

Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. - Vitor G. Lima; Guilherme Paim; Leandro M. G. Rocha; Leomar S. da Rosa Jr.; Felipe S. Marques 001; Eduardo A. C. da Costa; Vinícius V. Camargo; Rafael Soares; Sergio Bampi (ISCAS, 2019)

Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability. - Maicon Schneider Cardoso; Andrei A. O. Bubolz; Jordi Cortadella; Leomar Rosa; Felipe S. Marques 001 (ISCAS, 2020)

A Straightforward Methodology for QCA Circuits Design. - Julio Saraçol Domingues Júnior; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (SBCCI, 2020)

DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing. - Stéphano M. M. Gonçalves; Leomar S. da Rosa Jr.; Felipe de Souza Marques (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling. - Stephano Machado Moreira Goncalves; Leomar S. da Rosa Jr.; Felipe S. Marques 001 (ACM Trans. Design Autom. Electr. Syst., 2021)

Migortho: A Design Automation Flow for QCA Circuits. - Julio Saraçol Domingues Júnior; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (IEEE Des. Test, 2022)

Low-Code Microcontroller Programming: A Case Study with LoRa WAN Technology. - Samuel Santos Troina; Maiquel dos Santos Canabarro; Felipe de Souza Marques (LASCAS, 2025)