Transistor Sizing Analysis of Regular Fabrics. - Felipe S. Marranghello; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas; Francesc Moll (ARCS Workshops, 2011)

Impact and optimization of lithography-aware regular layout in digital circuit design. - Vinícius Dal Bem; Paulo F. Butzen; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ICCD, 2011)

Transistor sizing in lithography-aware regular fabrics. - Felipe S. Marranghello; Vinícius Dal Bem; André Inácio Reis; Francesc Moll; Renato P. Ribas (SBCCI, 2011)

Design-oriented delay model for CMOS inverter. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (SBCCI, 2012)

CMOS inverter delay model based on DC transfer curve for slow input. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ISQED, 2013)

Delay model for static CMOS complex gates. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (SBCCI, 2013)

Spin diode network synthesis using functional composition. - Mayler G. A. Martins; Felipe S. Marranghello; Joseph S. Friedman; Alan V. Sahakian; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

CMOS inverter analytical delay model considering all operating regions. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ISCAS, 2014)

Enhanced Spin-Diode Synthesis Using Logic Sharing. - Mayler G. A. Martins; Felipe S. Marranghello; Joseph S. Friedman; Alan V. Sahakian; Renato P. Ribas; André Inácio Reis (DSD, 2015)

Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. - Vinicius Callegaro; Felipe S. Marranghello; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (ICCD, 2015)

SOP based logic synthesis for memristive IMPLY stateful logic. - Felipe S. Marranghello; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (ICCD, 2015)

Improved logic synthesis for memristive stateful logic using multi-memristor implication. - Felipe S. Marranghello; Vinicius Callegaro; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas (ISCAS, 2015)

Fast buffer delay estimation considering time-dependent dielectric breakdown. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ISCAS, 2015)

Factored Forms for Memristive Material Implication Stateful Logic. - Felipe S. Marranghello; Vinicius Callegaro; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Performance evaluation of optimized transistor networks built using independent-gate FinFET. - Andres M. A. Valdes; Vinicius N. Possani; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (LASCAS, 2016)

Binary adder circuit design using emerging MIGFET devices. - Jeferson José Baqueta; Felipe S. Marranghello; Vinicius N. Possani; Augusto Neutzling; André Inácio Reis; Renato P. Ribas (ISQED, 2017)

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. - Vinícius Dal Bem; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (IEEE Trans. Emerg. Top. Comput., 2017)

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; André Inácio Reis; Renato P. Ribas (SBCCI, 2018)

One-Sided Countermeasures for Side-Channel Attacks Can Backfire. - Yang Yu 035; Felipe S. Marranghello; Victor Diges Teijeira; Elena Dubrova (WISEC, 2018)

Threshold Physical Unclonable Functions. - Felipe S. Marranghello; Yang Yu 035; Elena Dubrova (ISMVL, 2019)

Four-Level Forms for Memristive Material Implication Logic. - Felipe S. Marranghello; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (IEEE Trans. Very Large Scale Integr. Syst., 2019)

SAT-Sweeping Enhanced for Logic Synthesis. - Luca G. Amarù; Felipe S. Marranghello; Eleonora Testa; Christopher Casares; Vinicius N. Possani; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2020)

Exact Benchmark Circuits for Logic Synthesis. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; Pierre-Emmanuel Gaillardon; André Inácio Reis; Renato Perez Ribas (IEEE Des. Test, 2020)

maj-n Logic Synthesis for Emerging Technology. - Augusto Neutzling; Felipe S. Marranghello; Jody Maick Matos; André Inácio Reis; Renato P. Ribas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

LUT-Based Optimization For ASIC Design Flow. - Luca Gaetano Amarù; Vinicius N. Possani; Eleonora Testa; Felipe S. Marranghello; Christopher Casares; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2021)

A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations. - Cesar de S. Dias; Felipe S. Marranghello; Raphael Martins Brum; Paulo F. Butzen (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)