A Comparison of Virtual Platform Simulation Solutions for Timing Prediction of Small RISC-V Based SoCs. - Felix Böseler; Jörg Walter 001; Behnam Razi Perjikolaei (FDL, 2022)

A Flexible Graph Language for a Model-Based Semi-Automatic CGRA Compilation Flow. - Felix Böseler; Jörg Walter 001 (FDL, 2023)

Enabling Manual-Controllable Compilation for Dataflow CGRAs. - Felix Böseler; Jörg Walter 001; Verena Klös (IPDPS (Workshops), 2025)