Feng Lu

Affiliations:
  • Cadence Design Systems, USA
  • University of California, Santa Barbara, CA, USA (PhD 2006)


According to our database1, Feng Lu authored at least 12 papers between 2003 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
SEChecker: A Sequential Equivalence Checking Framework Based on Kth Invariants.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2007
Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
Pseudofunctional testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

IChecker: An Efficient Checker for Inductive Invariants.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005
Pseudo-Functional Scan-based BIST for Delay Fault.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Accurate Diagnosis of Multiple Faults.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Sequential equivalence checking based on k-th invariants and circuit SAT solving.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

An Efficient Sequential SAT Solver With Improved Search Strategies.
Proceedings of the 2005 Design, 2005

Constraint extraction for pseudo-functional scan-based delay testing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A Signal Correlation Guided Circuit-SAT Solver.
J. Univers. Comput. Sci., 2004

2003
A Circuit SAT Solver With Signal Correlation Guided Learning.
Proceedings of the 2003 Design, 2003

A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
Proceedings of the 40th Design Automation Conference, 2003


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