Feng Wang

Affiliations:
  • Qualcomm, Inc., San Diego, CA, USA
  • Penn State University, USA (PhD 2008)


According to our database1, Feng Wang authored at least 19 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2012
Fast cost efficient designs by building upon the plackett and burman method.
Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2012

Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

2011
Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model.
IEEE Trans. Dependable Secur. Comput., 2011

Variation-Aware Task and Communication Mapping for MPSoC Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2009
Process-Variation-Aware Adaptive Cache Architecture and Management.
IEEE Trans. Computers, 2009

Variation-aware resource sharing and binding in behavioral synthesis.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Design Space Exploration for 3-D Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A Variation Aware High Level Synthesis Framework.
Proceedings of the Design, Automation and Test in Europe, 2008

Variability-driven module selection with joint design time optimization and post-silicon tuning.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
On-chip bus thermal analysis and optimisation.
IET Comput. Digit. Tech., 2007

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Architecting Microprocessor Components in 3D Design Space.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Variation-aware task allocation and scheduling for MPSoC.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A novel criticality computation method in statistical timing analysis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Dependability Analysis of Nano-scale FinFET circuits.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

On-chip bus thermal analysis and optimization.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Optimal topology exploration for application-specific 3D architectures.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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