Optimal topology exploration for application-specific 3D architectures. - Ozcan Ozturk 001; Feng Wang 004; Mahmut T. Kandemir; Yuan Xie 001 (ASP-DAC, 2006)

On-chip bus thermal analysis and optimization. - Feng Wang 004; Yuan Xie 001; Narayanan Vijaykrishnan; Mary Jane Irwin (DATE, 2006)

Dependability Analysis of Nano-scale FinFET circuits. - Feng Wang 004; Yuan Xie 001; Kerry Bernstein; Yan Luo (ISVLSI, 2006)

Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design. - Xiaoxia Wu; Feng Wang 004; Yuan Xie 001 (SoCC, 2006)

A novel criticality computation method in statistical timing analysis. - Feng Wang 004; Yuan Xie 001; Hai Ju (DATE, 2007)

Variation-aware task allocation and scheduling for MPSoC. - Feng Wang 004; Chrysostomos Nicopoulos; Xiaoxia Wu; Yuan Xie 001; Narayanan Vijaykrishnan (ICCAD, 2007)

Architecting Microprocessor Components in 3D Design Space. - Balaji Vaidyanathan; Wei-Lun Hung; Feng Wang 004; Yuan Xie 001; Narayanan Vijaykrishnan; Mary Jane Irwin (VLSI Design, 2007)

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. - Feng Wang 004; Yuan Xie 001; R. Rajaraman; Balaji Vaidyanathan (VLSI Design, 2007)

On-chip bus thermal analysis and optimisation. - Feng Wang 004; Michael DeBole; Xiaoxia Wu; Yuan Xie 001; Narayanan Vijaykrishnan; Mary Jane Irwin (IET Comput. Digit. Tech., 2007)

Variability-driven module selection with joint design time optimization and post-silicon tuning. - Feng Wang 004; Xiaoxia Wu; Yuan Xie 001 (ASP-DAC, 2008)

A Variation Aware High Level Synthesis Framework. - Feng Wang 004; Guangyu Sun 003; Yuan Xie 001 (DATE, 2008)

Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations. - Feng Wang 004; Yuan Xie 001 (IPDPS, 2008)

Design Space Exploration for 3-D Cache. - Yuh-Fang Tsai; Feng Wang 004; Yuan Xie 001; Narayanan Vijaykrishnan; Mary Jane Irwin (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Variation-aware resource sharing and binding in behavioral synthesis. - Feng Wang 004; Yuan Xie 001; Andrés Takach (ASP-DAC, 2009)

Process-Variation-Aware Adaptive Cache Architecture and Management. - Madhu Mutyam; Feng Wang 004; Krishnan Ramakrishnan; Vijaykrishnan Narayanan; Mahmut T. Kandemir; Yuan Xie 001; Mary Jane Irwin (IEEE Trans. Computers, 2009)

Variation-Aware Task and Communication Mapping for MPSoC Architecture. - Feng Wang 004; Yibo Chen; Chrysostomos Nicopoulos; Xiaoxia Wu; Yuan Xie 001; Narayanan Vijaykrishnan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model. - Feng Wang 004; Yuan Xie 001 (IEEE Trans. Dependable Secur. Comput., 2011)

Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology. - Manish Arora; Feng Wang 004; Bob Rychlik; Dean M. Tullsen (ICSAMOS, 2012)

Fast cost efficient designs by building upon the plackett and burman method. - Manish Arora; Feng Wang 004; Bob Rychlik; Dean M. Tullsen (SIGMETRICS, 2012)