Search space reduction for the non-exact projective NPNP Boolean matching problem. - Feng Wang 046; Jiaxi Zhang 001; Lange Wu; Wentai Zhang 001; Guojie Luo (ISCAS, 2017)

V-PIM: An Analytical Overhead Model for Processing-in-Memory Architectures. - Peichen Xie; Guangyu Sun 003; Feng Wang 046; Guojie Luo (NVMSA, 2018)

Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Peng Huang 004; Jinfeng Kang (ASAP, 2019)

Dual-Output LUT Merging during FPGA Technology Mapping. - Feng Wang 046; Liren Zhu; Jiaxi Zhang 001; Lei Li; Yang Zhang; Guojie Luo (ICCAD, 2020)

Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning. - Jiaxi Zhang 001; Liwei Ni; Shenggen Zheng; Hao Liu; Xiangfu Zou; Feng Wang 046; Guojie Luo (ICCAD, 2021)

SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes. - Feng Wang 046; Guangyu Sun 003; Guojie Luo (ICCAD, 2021)

Area Efficient Pattern Representation of Binary Neural Networks on RRAM. - Feng Wang 046; Guojie Luo; Guang-Yu Sun 003; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (J. Comput. Sci. Technol., 2021)

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Jinfeng Kang; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)