A pipelined architecture for normal I/O order FFT. - Xue Liu 003; Feng Yu 003; Ze-ke Wang (J. Zhejiang Univ. Sci. C, 2011)

An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays. - Zhen-guo Ma; Feng Yu 003; Rui-feng Ge; Ze-ke Wang (J. Zhejiang Univ. Sci. C, 2011)

A Family of Fast Hadamard-Fourier Transform Algorithms. - Teng Su; Feng Yu 003 (IEEE Signal Process. Lett., 2012)

Block Processor: A resource-distributed architecture. - Ze-ke Wang; Feng Yu 003; Xue Liu 003 (HPEC, 2013)

Efficient Utilization of Vector Registers to Improve FFT Performance on SIMD Microprocessors. - Feng Yu 003; Rui-feng Ge; Ze-ke Wang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Efficient CORDIC-Based Processing Elements in Scalable Complex Matrix Inversion. - Huan He; Feng Yu 003; Bei Zhao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Radix-R WHT-FFT with Identical Stage-to-Stage Interconnection Pattern. - Qianjian Xing; Feng Yu 003; Xiaobo Yin; Bei Zhao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A Combinatorial Aliasing-Based Sparse Fourier Transform. - Pengcheng Qiu; Feng Yu 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Cloud-Friendly Communication-Optimal Implementation for Strassen's Matrix Multiplication Algorithm. - Jie Zhou; Feng Yu 003 (IEICE Trans. Inf. Syst., 2015)

An Optimum Architecture for Continuous-Flow Parallel Bit Reversal. - Chen Cheng; Feng Yu 003 (IEEE Signal Process. Lett., 2015)

Block Region of Interest Method for Real-Time Implementation of Large and Scalable Image Reconstruction. - Lin Li; Feng Yu 003 (IEEE Signal Process. Lett., 2015)

Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm. - Jinqi Liu; Qianjian Xing; Xiaobo Yin; Xiubin Mao; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm. - Zhen-guo Ma; Xiaobo Yin; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. - Ze-ke Wang; Xue Liu 003; Bingsheng He; Feng Yu 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A novel nonlinear equalizer for extending the dynamic range of analog-to-digital converters. - Xinfa Zhang; Feng Yu 003 (IEICE Electron. Express, 2016)

Time Delay Estimation via Co-Prime Aliased Sparse FFT. - Bei Zhao; Chen Cheng; Zhen-guo Ma; Feng Yu 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Efficient Circuit for Parallel Bit Reversal. - Weijun Li 001; Feng Yu 003; Zhen-guo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. - Xiaobo Yin; Feng Yu 003; Zhen-guo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Off-the-Grid Compressive Time Delay Estimation via Manifold-Based Optimization. - Wei Zhang 073; Feng Yu 003 (IEEE Commun. Lett., 2017)

Dynamic Parameterized $ ell _{1}$ -Regulation for Single-Snapshot DOA Estimations. - Wei Zhang 073; Feng Yu 003 (IEEE Commun. Lett., 2017)

Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy. - Tingting Chen; Weijun Li 001; Feng Yu 003; Qianjian Xing (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture. - Qianjian Xing; Zhen-guo Ma; Feng Yu 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Parameterized L1-Minimization Algorithm for Off-the-Gird Spectral Compressive Sensing. - Wei Zhang 073; Feng Yu 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Continuous-Flow Memory-Based Architecture for Real-Valued FFT. - Xiubin Mao; Zhen-guo Ma; Feng Yu 003; Qianjian Xing (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Fused Continuous Floating-Point MAC on FPGA. - Min Yuan; Qianjian Xing; Zhen-guo Ma; Feng Yu 003; Yingke Xu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Fast and Robust Diffusion Kurtosis Parametric Mapping Using a Three-Dimensional Convolutional Neural Network. - Zhiwei Li; Ting Gong; Zhichao Lin; Hongjian He; Qiqi Tong; Chen Li; Yi Sun; Feng Yu 003; Jianhui Zhong (IEEE Access, 2019)

Recurrent Highway Networks With Grouped Auxiliary Memory. - Wei Luo; Feng Yu 003 (IEEE Access, 2019)

Pipelined Algorithm and Modular Architecture for Matrix Transposition. - Yunxiang Wang; Zhen-guo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Resource-Efficient Parallel Tree-Based Join Architecture on FPGA. - Huan Zhang 004; Bei Zhao; Wei-Jun Li 001; Zhen-Guo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Sorting Matrix Architecture for Continuous Data Sequences. - Meiting Xue; Huan Zhang 004; Weijun Li 001; Feng Yu 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Learning longer-term dependencies via grouped distributor unit. - Wei Luo; Feng Yu 003 (Neurocomputing, 2020)

Multi-Branch Convolutional Neural Network for Automatic Sleep Stage Classification with Embedded Stage Refinement and Residual Attention Channel Fusion. - Tianqi Zhu; Wei Luo; Feng Yu 003 (Sensors, 2020)

A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA. - Weijie Chen 001; Weijun Li 001; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Modular Pipeline Architecture for Accelerating Join Operation in RDBMS. - Weijie Chen 001; Weijun Li 001; Feng Yu 003 (IEEE Trans. Circuits Syst., 2020)

High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA. - Wen-Qi Wu; Meiting Xue; Tian-Qi Zhu; Zhen-Guo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst., 2020)

FPGA-Accelerated Hash Join Operation for Relational Databases. - Meiting Xue; Qianjian Xing; Chen Feng; Feng Yu 003; Zhen-Guo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

High-Parallelism Hash-Merge Architecture for Accelerating Join Operation on FPGA. - Wen-Qi Wu; Meiting Xue; Qianjian Xing; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Novel Pipelined Algorithm and Modular Architecture for Non-Square Matrix Transposition. - Bo Zhang 097; Zhenguo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT. - Hongji Fang; Bo Zhang 097; Feng Yu 003; Bei Zhao; Zhenguo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Resource Efficient Top-K Sorter on FPGA. - Binhao He; Meiting Xue; Shubiao Liu; Feng Yu 003; Weijie Chen 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

General Adaptive Lossless Compression for Multi-Channel Sensor Signals. - Haori Zheng; Qianhao Chen; Feng Yu 003; Bo Zhang 097 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

HENCE: Hardware End-to-End Neural Conditional Entropy Encoder for Lossless 3D Medical Image Compression. - Jietao Chen; Qianhao Chen; Huan Zhang 004; Weijie Chen; Wei Luo; Feng Yu 003 (IEEE Access, 2024)

Optimised Serial Commutator FFT Architecture in Terms of Multiplexers. - Hongji Fang; Zhenguo Ma; Feng Yu 003; Bei Zhao; Bo Zhang 097 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

DTP-Net: Learning to Reconstruct EEG Signals in Time-Frequency Domain by Multi-Scale Feature Reuse. - Yan Pei 004; Jiahui Xu; Qianhao Chen; Chenhao Wang; Feng Yu 003; Lisan Zhang; Wei Luo (IEEE J. Biomed. Health Informatics, 2024)

Multi-Scale Contextual Coding for Human-Machine Vision of Volumetric Medical Images. - Jietao Chen; Weijie Chen; Qianjian Xing; Feng Yu 003 (IEEE Access, 2025)

A Pipelined Architecture for Interatomic Interactions Computation Considering Atomic Distribution. - Chengyang Han; Jifeng Luo; Yan Pei 004; Qianjian Xing; Feng Yu 003 (IEEE Access, 2025)

WaveSleepNet: An Interpretable Network for Expert-Like Sleep Staging. - Yan Pei 004; Jiahui Xu; Feng Yu 003; Lisan Zhang; Wei Luo (IEEE J. Biomed. Health Informatics, 2025)

Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform. - Kun Li 032; Hongji Fang; Zhenguo Ma; Feng Yu 003; Bo Zhang 097; Qianjian Xing (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Clementi: Efficient Load Balancing and Communication Overlap for Multi-FPGA Graph Processing. - Feng Yu 003; Hongshi Tan; Xinyu Chen 001; Yao Chen 008; Bingsheng He; Weng-Fai Wong (Proc. ACM Manag. Data, 2025)

A Fast Floating-Point Multiply-Accumulator Optimized for Sparse Linear Algebra on FPGAs. - Kun Li 032; Xiangyu Hao; Zhenguo Ma; Feng Yu 003; Bo Zhang 097; Qianjian Xing (IEEE Trans. Very Large Scale Integr. Syst., 2025)