A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection. - Yongpan Liu; Yu Wang 002; Feng Zhang 014; Rong Luo; Hui Wang 004 (APCCAS, 2006)

A High Speed CMOS Transmitter and Rail-to-Rail Receiver. - Feng Zhang 014; Zongren Yang; Wei Feng; Hao Cui; Lingyi Huang; Weiwu Hu (DELTA, 2008)

A 10Gb/s Wire-line Transceiver with Half Rate Period Calibration CDR. - Zhuo Gao; Hang Yu; Patrick Chiang 001; Yi Yang; Feng Zhang 014 (ISCAS, 2009)

A novel SST transmitter with mutually decoupled impedance self-calibration and equalization. - Shuai Chen; Liqiong Yang; Hua Jing; Feng Zhang 014; Zhuo Gao (ISCAS, 2011)

Sinusoidal Clock Sampling for Multigigahertz ADCs. - Rui Bai 001; Jingguang Wang; Lingli Xia; Feng Zhang 014; Zongren Yang; Weiwu Hu; Patrick Chiang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line. - Shuai Chen; Hao Li; Kai Jia; Yue Wang; Xiaobing Shi; Feng Zhang 014 (ISCAS, 2012)

An efficient physical coding sublayer for PCI express in 65nm CMOS. - Qihao Liu; Huihui Weng; Feng Zhang 014; Jianzhong Zhao; Junsheng Lv; You Li (ISPACS, 2012)

A novel equalizer for the high-loss backplane at Nyquist frequency. - You Li; Feng Zhang 014; Yumei Zhou (ASICON, 2013)

A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0. - Feng Zhang 014; Hao Ju; Chengying Chen (ASICON, 2015)

A 1V, 1.1mW mixed-signal hearing aid SoC in 0.13μm CMOS process. - Chengying Chen; Liming Chen 007; Jun Fan; Zenghui Yu; Jun Yang; Xiaoyu Hu; Yong Hei; Feng Zhang 014 (ISCAS, 2016)

A 128 Kb HfO2 ReRAM with Novel Double-Reference and Dynamic-Tracking scheme for write yield improvement. - Cheng-Ying Chen; Hongbin Sun 001; Haihua Shen; Feng Zhang 014 (IEICE Electron. Express, 2016)

A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection. - Chengying Chen; Liming Chen 007; Xinghua Wang; Feng Zhang 014 (ASICON, 2017)

An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects. - Yun Li; Haihua Shen; Ce Li; Feng Zhang 014 (ASICON, 2017)

A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. - Nan Qi; Yuhang Kang; Qipeng Lin; Jianxu Ma; Jingbo Shi; Bozhi Yin; Chang Liu; Rui Bai 001; Shang Hu; Juncheng Wang; Jiangbing Du; Lin Ma 008; et al. (A-SSCC, 2017)

A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range. - Feng Zhang 014; Dongyu Fan; Yuan Duan; Jin Li; Cong Fang 002; Yun Li; Xiaowei Han; Lan Dai; Cheng-Ying Chen; Jinshun Bi; Ming Liu 022; Meng-Fan Chang (A-SSCC, 2017)

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. - Xiaowei Han; Qian Jia; Hongbin Sun 001; Longfei Wang; Huaqiang Wu; Yimao Cai; Feng Zhang 014; Yongyi Xie; Fangxu Dong; Xiaoguang Wang 015; Xiaofei Xue; Li Pang; et al. (CICC, 2017)

Wide-range tracking technique for process-variation-robust clock and data recovery applications. - Junsheng Lv; You Li; Yumei Zhou; Jianzhong Zhao; Haihua Shen; Feng Zhang 014 (Frontiers Inf. Technol. Electron. Eng., 2017)

A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. - Chengying Chen; Liming Chen 007; Xinghua Wang; Feng Zhang 014 (ISCAS, 2018)

The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory. - Feng Zhang 014; Dongyu Fan; Qi-Peng Lin; Qiang Huo; Yun Li; Lan Dai; Cheng-Ying Chen; Haihua Shen (VLSI-DAT, 2018)

A 0.6V, 8.4uW AFE circuit for biomedical signal recording. - Chengying Chen; Liming Chen 007; Xinghua Wang; Feng Zhang 014 (Microelectron. J., 2018)

LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. - Haihua Shen; Huazhe Tan; Huawei Li 001; Feng Zhang 014; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Adaptive Power Optimization for Mobile Traffic Based on Machine Learning. - Wei Zhao; Haihua Shen; Feng Zhang 014; Huazhe Tan (CSCWD, 2019)

Particle Swarm Optimization for Great Enhancement in Semi-supervised Retinal Vessel Segmentation with Generative Adversarial Networks. - Qiang Huo; Geyu Tang; Feng Zhang 014 (MLMECH/CVII-STENT@MICCAI, 2019)

A Modeling Approach for 7nm Technology Node Area-Consuming Circuit Optimization and Beyond. - Qiang Huo; Zhenhua Wu; Feng Zhang 014; Ling Li 013 (SMACD, 2019)

A Fluctuation Model of a Hf02 RRAM Cell for Memory Circuit Designs. - Feng Zhang 014; Linan Li; Qiang Huo; Cong Fang 002; Wenqiang Ba (SMACD, 2019)

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond. - Qiang Huo; Zhenhua Wu; Weixing Huang; Xingsheng Wang; Geyu Tang; Jiaxin Yao; Yongpan Liu; Feng Zhang 014; Ling Li 013; Ming Liu 022 (CoRR, 2019)

HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. - Renjie Lu; Haihua Shen; Feng Zhang 014; Huawei Li 001; Wei Zhao; Xiaowei Li 001 (CoRR, 2019)

A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications. - Yiming Wang; Yun Li; Haihua Shen; Dongyu Fan; Wei Wang 003; Ling Li 013; Qi Liu 010; Feng Zhang 014; Xinghua Wang; Meng-Fan Chang; Ming Liu 022 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques. - Jianguo Yang; Xiaoyong Xue; Xiaoxin Xu; Hangbing Lv; Feng Zhang 014; Xiaoyang Zeng; Meng-Fan Chang; Ming Liu 022 (VLSI Circuits, 2020)

A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications. - Fei Tan; Yiming Wang; Yiming Yang; Liran Li; Tian Wang; Feng Zhang 014; Xinghua Wang; Jianfeng Gao 005; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise. - Qiang Zhao; Wenhan Zheng; Xiaojin Zhao; Yuan Cao 003; Feng Zhang 014; Man-Kay Law (IEEE Trans. Circuits Syst., 2020)

24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m2 Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference. - Jianguo Yang; Xiaoyong Xue; Xiaoxin Xu; Qiao Wang; Haijun Jiang; Jie Yu 027; Danian Dong; Feng Zhang 014; Hangbing Lv; Ming Liu 022 (ISSCC, 2021)

Investigation of weight updating modes on oxide-based resistive switching memory synapse towards neuromorphic computing applications. - Qingting Ding; Tiancheng Gong; Jie Yu 027; Xiaoxin Xu; Xiaoyan Li; Hangbing Lv; Jianguo Yang; Qing Luo; Peng Yuan; Feng Zhang 014; Ming Liu 022 (Sci. China Inf. Sci., 2021)

Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control. - Linfang Wang; Wang Ye; Chunmeng Dou; Xin Si; Xiaoxin Xu; Jing Liu 035; Dashan Shang; Jianfeng Gao 005; Feng Zhang 014; Yongpan Liu; Meng-Fan Chang; Qi Liu 010 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection. - Qirui Ren; Chengying Chen; Danian Dong; Xiaoxin Xu; Yong Chen 005; Feng Zhang 014 (Sensors, 2022)

Fast and Reconfigurable Logic Synthesis in Memristor Crossbar Array. - Wei Wang 003; Sen Liu 006; Qingjiang Li; Tuo Shi; Feng Zhang 014; Haijun Liu 003; Nan Li 020; Yongzhou Wang; Yi Sun; Bing Song; Hui Xu 010; Qi Liu 010 (Adv. Intell. Syst., 2022)

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. - Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; Yongpan Liu; et al. (ISSCC, 2023)

A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. - Qirui Ren; Qiang Huo; Zhisheng Chen; Qi Gao; Yiming Wang; Yiming Yang; Hao Wu 084; Xiangqu Fu; Xiaoxin Xu; Qing Luo; Jianfeng Gao 005; Chengying Chen; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. - Wang Ye; Linfang Wang; Zhidao Zhou; Junjie An; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinshan Yue; Hongyang Hu; Xiaoxin Xu; Jianguo Yang; Jing Liu 035; et al. (IEEE J. Solid State Circuits, 2023)

P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer. - Xiangqu Fu; Qirui Ren; Hao Wu 084; Feibin Xiang; Qing Luo; Jinshan Yue; Yong Chen 005; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC. - Yiyang Yuan; Yiming Yang; Xinghua Wang; Xiaoran Li; Cailian Ma; Qirui Chen; Meini Tang; Xi Wei; Zhixian Hou; Jialiang Zhu; Hao Wu 084; Qirui Ren; et al. (ISSCC, 2024)

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications. - Zhuoyu Dai; Shengzhe Yan; Zhaori Cong; Zeyu Guo 002; Yifan He 002; Wenyu Sun; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu; Ming Liu 022 (VLSI Technology and Circuits, 2024)

A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. - Hao Wu 084; Yong Chen 005; Yiyang Yuan; Jinshan Yue; Xiangqu Fu; Qirui Ren; Qing Luo; Pui-In Mak; Xinghua Wang; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. - Shengzhe Yan; Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; et al. (IEEE J. Solid State Circuits, 2024)

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices. - Zhuoyu Dai; Feibin Xiang; Xiangqu Fu; Yifan He 003; Wenyu Sun; Yongpan Liu; Guanhua Yang; Feng Zhang 014; Jinshan Yue; Ling Li 013 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference. - Yiyang Yuan; Bingxin Zhang; Yiming Yang; Yishan Luo; Qirui Chen; Shidong Lv; Hao Wu 084; Cailian Ma; Ming Li; Jinshan Yue; Xinghua Wang; Guozhong Xing; et al. (ISSCC, 2025)

A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity. - Hao Wu 084; Yong Chen 005; Yiyang Yuan; Jinshan Yue; Xinghua Wang; Xiaoran Li; Feng Zhang 014 (IEEE J. Solid State Circuits, 2025)

A 28 nm 75.6 KOPS 13 nJ Computing-in-Memory Pipeline Number Theoretic Transform Accelerator for PQC. - Jialiang Zhu; Yiyang Yuan; Long Nie; Weiye Tang; Ming Li; Hao Wu 084; Xiaojin Zhao; Guozhong Xing; Feng Zhang 014 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer. - Xiangqu Fu; Jinshan Yue; Muhammad Faizan; Zhi Li 062; Qiang Huo; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet. - Zhihang Qian; Shengzhe Yan; Zhuoyu Dai; Zeyu Guo 002; Zhaori Cong; Yifan He 002; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications. - Jun Wang; Shengzhe Yan; Xiangqu Fu; Zhihang Qian; Zhi Li 062; Zeyu Guo 002; Zhuoyu Dai; Zhaori Cong; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Dashan Shang (IEEE Trans. Very Large Scale Integr. Syst., 2025)