RNA: a reconfigurable architecture for hardware neural acceleration. - Fengbin Tu; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (DATE, 2015)

Neural approximating architecture targeting multiple application domains. - Fengbin Tu; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (ISCAS, 2015)

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs. - Shibin Tang; Shouyi Yin; Shixuan Zheng; Peng Ouyang; Fengbin Tu; Leiyue Yao; JinZhou Wu; Wenming Cheng; Leibo Liu; Shaojun Wei (NVMSA, 2017)

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. - Fengbin Tu; Shouyi Yin; Peng Ouyang; Shibin Tang; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2017)

LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. - Xinhan Lin; Shouyi Yin; Fengbin Tu; Leibo Liu; Xiangyu Li; Shaojun Wei (DAC, 2018)

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. - Fengbin Tu; Weiwei Wu; Shouyi Yin; Leibo Liu; Shaojun Wei (ISCA, 2018)

Bit-width Adaptive Accelerator Design for Convolution Neural Network. - Jianxin Guo; Shouyi Yin; Peng Ouyang; Fengbin Tu; Shibin Tang; Leibo Liu; Shaojun Wei (ISCAS, 2018)

An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. - Zhihui Wang; Shouyi Yin; Fengbin Tu; Leibo Liu; Shaojun Wei (ISCAS, 2018)

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. - Shouyi Yin; Peng Ouyang; Shibin Tang; Fengbin Tu; Xiudong Li; Shixuan Zheng; Tianyi Lu; Jiangyuan Gu; Leibo Liu; Shaojun Wei (IEEE J. Solid State Circuits, 2018)

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration. - Jiale Yan; Shouyi Yin; Fengbin Tu; Leibo Liu; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Towards Efficient Compact Network Training on Edge-Devices. - Feng Xiong; Fengbin Tu; Shouyi Yin; Shaojun Wei (ISVLSI, 2019)

MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions. - Weiwei Wu; Shouyi Yin; Fengbin Tu; Leibo Liu; Shaojun Wei (NEWCAS, 2019)

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. - Shouyi Yin; Shibin Tang; Xinhan Lin; Peng Ouyang; Fengbin Tu; Leibo Liu; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Reconfigurable Architecture for Neural Approximation in Multimedia Computing. - Fengbin Tu; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (IEEE Trans. Circuits Syst. Video Technol., 2019)

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. - Shouyi Yin; Shibin Tang; Xinhan Lin; Peng Ouyang; Fengbin Tu; Leibo Liu; Jishen Zhao; Cong Xu 002; Shuangchen Li; Yuan Xie 001; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2019)

STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. - Feng Xiong; Fengbin Tu; Man Shi; Yang Wang 089; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2020)

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture. - Liu Liu 017; Zheng Qu; Lei Deng 003; Fengbin Tu; Shuangchen Li; Xing Hu 001; Zhenyu Gu; Yufei Ding 001; Yuan Xie 001 (MICRO, 2020)

ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training. - Xinhan Lin; Liang Sun; Fengbin Tu; Leibo Liu; Xiangyu Li; Shaojun Wei; Shouyi Yin (DAC, 2021)

Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper. - Hussam Amrouch; Jian-Jia Chen; Kaushik Roy 001; Yuan Xie 001; Indranil Chakraborty; Wenqin Huangfu; Ling Liang; Fengbin Tu; Cheng Wang 036; Mikail Yayla (ICCAD, 2021)

Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. - Fengbin Tu; Weiwei Wu; Yang Wang 089; Hongjiang Chen; Feng Xiong; Man Shi; Ning Li; Jinyi Deng; Tianbao Chen; Leibo Liu; Shaojun Wei; Yuan Xie 001; et al. (IEEE J. Solid State Circuits, 2021)

Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning". - Fengbin Tu; Weiwei Wu; Yang Wang 089; Hongjiang Chen; Feng Xiong; Man Shi; Ning Li; Jinyi Deng; Tianbao Chen; Leibo Liu; Shaojun Wei; Yuan Xie 001; et al. (IEEE J. Solid State Circuits, 2021)

DOTA: detect and omit weak attentions for scalable transformer acceleration. - Zheng Qu; Liu Liu 017; Fengbin Tu; Zhaodong Chen; Yufei Ding 001; Yuan Xie 001 (ASPLOS, 2022)

Alleviating datapath conflicts and design centralization in graph analytics acceleration. - Haiyang Lin; Mingyu Yan; Duo Wang; Mo Zou; Fengbin Tu; Xiaochun Ye; Dongrui Fan; Yuan Xie 001 (DAC, 2022)

Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU. - Ling Liang; Zhaodong Chen; Lei Deng 003; Fengbin Tu; Guoqi Li; Yuan Xie 001 (DATE, 2022)

INSPIRE: in-storage private information retrieval via protocol and architecture co-design. - Jilan Lin; Ling Liang; Zheng Qu; Ishtiyaque Ahmad; Liu Liu 017; Fengbin Tu; Trinabh Gupta; Yufei Ding 001; Yuan Xie 001 (ISCA, 2022)

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Ling Liang; Yufei Ding 001; Bongjin Kim; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (ISSCC, 2022)

A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Ling Liang; Liu Liu 017; Yufei Ding 001; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (ISSCC, 2022)

Dynamic Sparse Attention for Scalable Transformer Acceleration. - Liu Liu 017; Zheng Qu; Zhaodong Chen; Fengbin Tu; Yufei Ding 001; Yuan Xie 001 (IEEE Trans. Computers, 2022)

H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks. - Ling Liang; Zheng Qu; Zhaodong Chen; Fengbin Tu; Yujie Wu 002; Lei Deng 003; Guoqi Li; Peng Li 001; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating. - Jianxun Yang; Fengbin Tu; Yixuan Li; Yiqi Wang 005; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

AutoDCIM: An Automated Digital CIM Compiler. - Jia Chen; Fengbin Tu; Kunming Shao; Fengshi Tian; Xiao Huo; Chi-Ying Tsui; Kwang-Ting Cheng (DAC, 2023)

PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural Network Accelerators. - Yu Zhu; Zhenhua Zhu; Guohao Dai; Fengbin Tu; Hanbo Sun; Kwang-Ting Cheng; Huazhong Yang; Yu Wang 002 (DAC, 2023)

BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare. - Fengshi Tian; Xiaomeng Wang; Jinbo Chen; Jiakun Zheng; Hui Wu 010; Xuejiao Liu; Fengbin Tu; Jie Yang 033; Mohamad Sawan; Chi-Ying Tsui; Kwang-Ting (Tim) Cheng (ESSCIRC, 2023)

ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification. - Siqi Li; Fengbin Tu; Liu Liu 017; Jilan Lin; Zheng Wang 075; Yangwook Kang; Yufei Ding 001; Yuan Xie 001 (ISCA, 2023)

MuITCIM: A 28nm $2.24 mu mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (ISSCC, 2023)

TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (ISSCC, 2023)

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Boxiao Han; Hongjun He; Fengbin Tu; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (MICRO, 2023)

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Fengbin Tu; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (CoRR, 2023)

A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications. - Xiaomeng Wang; Fengshi Tian; Xizi Chen; Jiakun Zheng; Xuejiao Liu; Fengbin Tu; Jie Yang 033; Mohamad Sawan; Kwang-Ting Cheng; Chi-Ying Tsui (CoRR, 2023)

TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Ling Liang; Liu Liu 017; Yufei Ding 001; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Ling Liang; Yufei Ding 001; Bongjin Kim; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

SPG: Structure-Private Graph Database via SqueezePIR. - Ling Liang; Jilan Lin; Zheng Qu; Ishtiyaque Ahmad; Fengbin Tu; Trinabh Gupta; Yufei Ding 001; Yuan Xie 001 (Proc. VLDB Endow., 2023)

SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. - Fengbin Tu; Yiqi Wang 005; Ling Liang; Yufei Ding 001; Leibo Liu; Shaojun Wei; Shouyi Yin; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition. - Weiwei Wu; Fengbin Tu; Mengqi Niu; Zhiheng Yue; Leibo Liu; Shaojun Wei; Xiangyu Li; Yang Hu 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. - Yiqi Wang 005; Fengbin Tu; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips. - Shaojun Wei; Xinhan Lin; Fengbin Tu; Yang Wang 089; Leibo Liu; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive Posit. - Jingyu He; Fengbin Tu; Kwang-Ting Cheng; Chi-Ying Tsui (DATE, 2024)

Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. - Zhiheng Yue; Huizheng Wang; Jiahao Fang; Jinyi Deng; Guangyang Lu; Fengbin Tu; Ruiqi Guo; Yuxuan Li; Yubin Qin; Yang Wang 089; Chao Li 009; Huiming Han; et al. (ISCA, 2024)

20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. - Ruiqi Guo; Lei Wang; Xiaofeng Chen; Hao Sun; Zhiheng Yue; Yubin Qin; Huiming Han; Yang Wang 089; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. - Zhiheng Yue; Xujiang Xiang; Fengbin Tu; Yang Wang 089; Yiming Wang; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming. - Maolin Wang 002; Ian McInerney; Bartolomeo Stellato; Fengbin Tu; Stephen P. Boyd; Hayden Kwok-Hay So; Kwang-Ting Cheng (MICRO, 2024)

ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. - Yiqi Wang 005; Zhen He; Chenggang Zhao; Zihan Wu 006; Mingyu Gao 001; Huiming Han; Shaojun Wei; Yang Hu 001; Fengbin Tu; Shouyi Yin (VLSI Technology and Circuits, 2024)

A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation. - Ruiqi Guo; Xiaofeng Chen; Lei Wang; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

SWG: an architecture for sparse weight gradient computation. - Weiwei Wu; Fengbin Tu; Xiangyu Li; Shaojun Wei; Shouyi Yin (Sci. China Inf. Sci., 2024)

MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (IEEE J. Solid State Circuits, 2024)

HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques. - Xin Zhao 044; Liang Chang 002; Dongqi Fan; Zhicheng Hu; Ting Yue; Fengbin Tu; Jun Zhou 017 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference. - Jiajun Zhou; Jiajun Wu 006; Yizhao Gao 002; Yuhao Ding; Chaofan Tao; Boyu Li; Fengbin Tu; Kwang-Ting Cheng; Hayden Kwok-Hay So; Ngai Wong 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture. - Weiwei Wu; Fengbin Tu; Shaojun Wei; Xiangyu Li; Yang Hu 001; Shouyi Yin (ASAP, 2025)

SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. - Kunming Shao; Fengshi Tian; Xiaomeng Wang; Jiakun Zheng; Jia Chen; Jingyu He; Hui Wu 010; Jinbo Chen; Xihao Guan; Yi Deng; Fengbin Tu; Jie Yang 033; et al. (DATE, 2025)

ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. - Zhen He; Yiqi Wang 005; Zihan Wu 006; Shaojun Wei; Yang Hu 001; Fengbin Tu; Shouyi Yin (HPCA, 2025)

A 28nm 0.22μJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation. - Pingcheng Dong; Yonghao Tan; Xuejiao Liu; Peng Luo; Yu Liu 007; Luhong Liang; Yitong Zhou; Di Pang; Manto Yung; Dong Zhang; Xijie Huang; Shih-Yang Liu; et al. (ISSCC, 2025)

Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE Trans. Computers, 2025)

TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration. - Yiqi Wang 005; Zihan Wu 006; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Fengbin Tu; Shouyi Yin (IEEE J. Solid State Circuits, 2025)

CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction. - Zhiheng Yue; Yang Wang 089; Huizheng Wang; Ruiqi Guo; Fengbin Tu; Jianxun Yang; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2025)