A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators. - Yujun Shu; Fengyi Mei; Youling Yu; Jiangfeng Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs. - Yunchuan Wang; Li Zhang; Fengyi Mei; Yongzhen Chen; Jiangfeng Wu (ASICON, 2021)

An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC. - Li Zhang; Yunchuan Wang; Fengyi Mei; Yongzhen Chen; Jiangfeng Wu (ASICON, 2021)

A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver. - Jun Chen; Fengyi Mei; Mingzhe Liu; Yongzhen Chen; Jiangfeng Wu (ASICON, 2023)

Pipelined-SAR ADC Calibration Technique Based on Gain-Bit Weights. - Hang Ling; Yifei Bai; Fengyi Mei; Huajun Yao; Yongzhen Chen; Jiangfeng Wu (ASICON, 2023)

A Rapid Binary Search-Based Capacitor Mismatch Calibration Algorithm. - Yifei Bai; Huajun Yao; Fengyi Mei; Cuixia Wang; Yongzhen Chen; Jiangfeng Wu (ISCAS, 2025)