Pre-silicon Noise to Timing Test Methodology. - Fern Nee Tan; Jia Yun Chuah (ATS, 2020)

Power Integrity Specification Definition for an Integrated Clock Circuit Design. - Fern Nee Tan; Mohamad Shahrir Tamrin; Jia Yun Chuah (ISOCC, 2021)

Determining PCIe5 Jitter Margin using SIPI Co-Sim. - Fern Nee Tan; Li Wern Chew; Ling Li Ong (ISOCC, 2022)