A strategy for testability enhancement at layout level. - João Paulo Teixeira 001; Isabel C. Teixeira; Carlos F. Beltrán Almeida; Fernando M. Gonçalves; Júlio Gonçalves; R. Crespo (EURO-DAC, 1990)

IC Defects-Based Testability Analysis. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001 (ITC, 1991)

A methodology for testability enhancement at layout level. - João Paulo Teixeira 001; Isabel C. Teixeira; Carlos F. Beltrán Almeida; Fernando M. Gonçalves; Júlio Gonçalves (J. Electron. Test., 1991)

Physical design of testable CMOS digital integrated circuits. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001 (IEEE J. Solid State Circuits, 1991)

Physical DFT for High Coverage of Realistic Faults. - M. Saraiva; P. Casimiro; Marcelino B. Santos; José T. de Sousa; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 1992)

On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. - A. P. Casimiro; Fernando M. Gonçalves; João Paulo Teixeira 001; Marcelino B. Santos (DFT, 1994)

Fault Modeling and Defect Level Projections in Digital ICs. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001; Thomas W. Williams (EDAC-ETC-EUROASIC, 1994)

Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. - Mario Calha; Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 1994)

Integrated Approach for Circuit and Fault Extraction of VLSI Circuits. - Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 1996)

Defect level evaluation in an IC design environment. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001; Cristoforo Marzocca; Francesco Corsi; Thomas W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. - Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 1997)

Defect-oriented testing of analogue and mixed signal ICs. - Marcelino B. Santos; Fernando M. Gonçalves; Michael J. Ohletz; João Paulo Teixeira 001 (ICECS, 1998)

Defect-oriented test quality assessment using fault sampling and simulation. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 1998)

Sampling Techniques of Non-Equally Probable Faults in VLSI System. - Fernando M. Gonçalves; João Paulo Teixeira 001 (VTS, 1998)

Teaching Microelectronic-Based Integrated Systems Design and Test. - Fernando M. Gonçalves; João Paulo Teixeira 001 (MSE, 1999)

Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. - Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (VTS, 1999)

Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems. - Fernando M. Gonçalves; João Paulo Teixeira 001 (J. Electron. Test., 1999)

RTL-based functional test generation for high defects coverage in digital SOCs. - Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (ETW, 2000)

Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTW, 2001)

Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 2001)

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. - Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Electron. Test., 2001)

Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 2002)

DARP - A Digital Audio Reconfigurable Processor. - José T. de Sousa; Fernando M. Gonçalves; Nuno Barreiro; João Moura 002 (FPL, 2002)

Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Electron. Test., 2002)

RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. - Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Electron. Test., 2002)

Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2003)

A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. - Victor Gonçalves; José T. de Sousa; Fernando M. Gonçalves (FPL, 2005)

On-Detector Electronics of the Clear PEM Scanner. - Edgar F. M. Albuquerque; Vasco Bexiga; Ricardo Bugalho; Bruno Carriço; Cláudia S. Ferreira; Miguel Ferreira; Joaquim Godinho; Fernando M. Gonçalves; Carlos Leong; Pedro Lousã; Pedro Machado; Rui Moura; et al. (BIODEVICES, 2009)

Hardware/software specialization through aspects: The LARA approach. - João M. P. Cardoso; Tiago Carvalho 001; João Teixeira; Pedro C. Diniz; Fernando M. Gonçalves; Zlatko Petrov (ICSAMOS, 2012)

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain. - Razvan Nane; Vlad Mihai Sima; Cuong Pham-Quoc; Fernando M. Gonçalves; Koen Bertels (EUC, 2014)

Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach. - João M. P. Cardoso; José Gabriel F. Coutinho; Tiago Carvalho 001; Pedro C. Diniz; Zlatko Petrov; Wayne Luk; Fernando M. Gonçalves (Softw. Pract. Exp., 2016)

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. - Luís Fiolhais; Fernando M. Gonçalves; Rui Policarpo Duarte; Mário P. Véstias; José T. de Sousa (ISCAS, 2019)