A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (FPL, 2008)

A Versatile Linear Insertion Sorter Based on a FIFO Scheme. - Roberto Perez-Andrade; René Cumplido; Fernando Martin del Campo; Claudia Feregrino Uribe (ISVLSI, 2008)

Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. - Fernando Martin del Campo; René Cumplido; Roberto Perez-Andrade; Aldo G. Orozco-Lugo (ReConFig, 2008)

A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation. - Fernando Martin del Campo; René Cumplido; Roberto Perez-Andrade; Aldo G. Orozco-Lugo (Int. J. Reconfigurable Comput., 2009)

A versatile linear insertion sorter based on an FIFO scheme. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (Microelectron. J., 2009)

A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (Digit. Signal Process., 2010)

A multi-cycle fixed point square root module for FPGAs. - Fernando Martin del Campo; Alicia Morales-Reyes; Roberto Perez-Andrade; René Cumplido; Aldo G. Orozco-Lugo; Claudia Feregrino (IEICE Electron. Express, 2012)

Architecture Exploration for Data Intensive Applications. - Fernando Martin del Campo; Paul Chow (MEMSYS, 2015)

Task replication and control for highly parallel in-memory stores. - Fernando Martin del Campo; Paul Chow (MEMSYS, 2017)