CReconfigurable finite field instruction set architecture. - Nathan Jachimiec; Fernando Martinez-Vallina; Jafar Saniie (FPGA, 2007)

Image and video processing platform for field programmable gate arrays using a high-level synthesis. - Christophe Desmouliers; Erdal Oruklu; Semih Aslan; Jafar Saniie; Fernando Martinez-Vallina (IET Comput. Digit. Tech., 2012)

Building zynq® accelerators with Vivado® high level synthesis. - Stephen Neuendorffer; Fernando Martinez-Vallina (FPGA, 2013)

Unlocking FPGAs Using High Level Synthesis Compiler Technologies. - Fernando Martinez-Vallina; Henry Styles (FPGA, 2015)

OpenCL library of stream memory components targeting FPGAs. - Jasmina Vasiljevic; Ralph Wittig; Paul Schumacher; Jeff Fifield; Fernando Martinez-Vallina; Henry Styles; Paul Chow (FPT, 2015)

Performance optimization for a SHA-1 cryptographic workload expressed in OpenCL for FPGA execution. - Fernando Martinez-Vallina; Spenser Gilliland (IWOCL, 2015)

Developing optimized libraries for scalable OpenCL acceleration on FPGAs. - Fernando Martinez-Vallina; Devadas Varma; Vinay Singh (IWOCL, 2015)

Implementation of elementary functions for FPGA compute accelerators. - Spenser Gilliland; Jafar Saniie; Fernando Martinez-Vallina (EIT, 2016)

Analysis of library functions for FPGA compute accelerators. - Spenser Gilliland; Jafar Saniie; Fernando Martinez-Vallina (EIT, 2017)