Modeling and Evaluation of Substrate Noise Induced by Interconnects. - Ferran Martorell; Diego Mateo; Xavier Aragonès (DATE, 2003)

A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation. - Luis Elvira; Ferran Martorell; Xavier Aragonès; José Luis González 001 (DATE, 2004)

A physical-based noise macromodel for fast simulation of switching noise generation. - Luis Elvira; Ferran Martorell; Xavier Aragonès; José Luis González 001 (Microelectron. J., 2004)

Discrete and continuous substrate noise spectrum dependence on digital circuit characteristics. - Enrique Barajas; Luis Elvira; Miguel A. Méndez; Ferran Martorell; Diego Mateo; José Luis González 001 (ISCAS (5), 2005)

Power supply noise and logic error probability. - Dennis Andrade; Ferran Martorell; Marc Pons 001; Francesc Moll; Antonio Rubio 001 (ECCTD, 2007)

Cell architecture for nanoelectronic design. - Ferran Martorell; Antonio Rubio 001 (Microelectron. J., 2008)

A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs. - Dennis Andrade; Ferran Martorell; Antonio Calomarde; Francesc Moll; Antonio Rubio 001 (Microelectron. J., 2009)

RTL-Aware Dataflow-Driven Macro Placement. - Alex Vidal-Obiols; Jordi Cortadella; Jordi Petit; Marc Galceran Oms; Ferran Martorell (DATE, 2019)

Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods. - Alex Vidal-Obiols; Jordi Cortadella; Jordi Petit; Marc Galceran Oms; Ferran Martorell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)