Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode. - Filip Tavernier; Michiel Steyaert (ESSCIRC, 2008)

A high-speed fully integrated optical receiver in standard 130nm CMOS. - Filip Tavernier; Michiel Steyaert (ICECS, 2008)

A low power, area efficient limiting amplifier in 90nm CMOS. - Filip Tavernier; Michiel Steyaert (ESSCIRC, 2009)

High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS. - Filip Tavernier; Michel S. J. Steyaert (IEEE J. Solid State Circuits, 2009)

A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode. - Filip Tavernier; Michiel Steyaert (ESSCIRC, 2010)

When hardware is free, power is expensive! Is integrated power management the solution? - Michiel Steyaert; Filip Tavernier; Hans Meyvaert; Athanasios Sarafianos; Nicolas Butzen (ESSCIRC, 2015)

10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS. - Tao Zhang 034; Ping Gui; Sudipto Chakraborty; Tianwei Liu; Guoying Wu; Paulo Moreira; Filip Tavernier (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS. - Athanasios Ramkaj; Maarten Strackx; Michiel Steyaert; Filip Tavernier (ESSCIRC, 2017)

Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers. - Wouter Diels; Michiel Steyaert; Filip Tavernier (ESSDERC, 2017)

Schottky diodes in 40nm bulk CMOS for 1310nm high-speed optical receivers. - Wouter Diels; Michiel Steyaert; Filip Tavernier (OFC, 2017)

A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS. - Tim Thielemans; Nicolas Butzen; Athanasios Sarafianos; Michiel Steyaert; Filip Tavernier (CICC, 2018)

A 1310/1550 nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40 nm Bulk CMOS. - Wouter Diels; Michiel Steyaert; Filip Tavernier (ESSCIRC, 2018)

A Charge-Sharing Bandpass Filter Topology with Boosted Q-Factor in 40-NM CMOS. - Filipe D. Baumgratz; Sandro B. Ferreira; Michiel Steyaert; Sergio Bampi; Filip Tavernier (SBCCI, 2018)

A 400GΩ Input-Impedance, 220MVpp Linear-Input-Range, 2.8Vpp CM-Interference-Tolerant Active Electrode for Non-Contact Capacitively Coupled ECG Acquisition. - Mingyi Chen; Ivan Dario Castro; Qiuyang Lin; Tom Torfs; Filip Tavernier; Chris Van Hoof; Nick Van Helleputte (VLSI Circuits, 2018)

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS. - Athanasios Ramkaj; Maarten Strackx; Michiel S. J. Steyaert; Filip Tavernier (IEEE J. Solid State Circuits, 2018)

40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor. - Filipe D. Baumgratz; Sandro Binsfeld Ferreira; Michiel S. J. Steyaert; Sergio Bampi; Filip Tavernier (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Optical Receiver with Schottky Photodiode and TIA with High Gain Amplifier in 28nm Bulk CMOS. - Wouter Diels; Michiel Steyaert; Filip Tavernier (ESSCIRC, 2019)

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs. - Yifan Lyu; Filip Tavernier (ESSCIRC, 2019)

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS. - Athanasios T. Ramkaj; Michiel S. J. Steyaert; Filip Tavernier (ESSCIRC, 2019)

A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS. - Athanasios Ramkaj; Juan Carlos Pena Ramos; Yifan Lyu; Maarten Strackx; Marcel J. M. Pelgrom; Michiel Steyaert; Marian Verhelst; Filip Tavernier (ISSCC, 2019)

A Fully-Integrated 6: 1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm2. - Tuur Van Daele; Elly De Pelecijn; Tim Thielemans; Michiel Steyaert; Filip Tavernier (PRIME, 2019)

A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors. - Qiuyang Lin; Jiawei Xu 001; Shuang Song 003; Arjan Breeschoten; Mario Konijnenburg; Mingyi Chen; Chris Van Hoof; Filip Tavernier; Nick Van Helleputte (VLSI Circuits, 2019)

A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS. - Filipe D. Baumgratz; Carlos E. Saavedra; Michiel Steyaert; Filip Tavernier; Sergio Bampi (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 1 GS/s Reconfigurable BW 2nd-Order Noise-Shaping Hybrid Voltage-Time Two-Step ADC Achieving 170.9 dB FoMS. - Yifan Lyu; Filip Tavernier (VLSI Circuits, 2020)

A 4V-0.55V Input Fully Integrated Switched-Capacitor Converter Enabling Dynamic Voltage Domain Stacking and Achieving 80.1% Average Efficiency. - Tim Thielemans; Filip Tavernier (VLSI Circuits, 2020)

1310/1550 nm Optical Receivers With Schottky Photodiode in Bulk CMOS. - Wouter Diels; Michiel Steyaert; Filip Tavernier (IEEE J. Solid State Circuits, 2020)

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs. - Yifan Lyu; Filip Tavernier (IEEE J. Solid State Circuits, 2020)

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS. - Athanasios T. Ramkaj; Juan Carlos Pena Ramos; Marcel J. M. Pelgrom; Michiel S. J. Steyaert; Marian Verhelst; Filip Tavernier (IEEE J. Solid State Circuits, 2020)

A 119dB Dynamic Range Charge Counting Light-to-Digital Converter For Wearable PPG/NIRS Monitoring Applications. - Qiuyang Lin; Jiawei Xu 001; Shuang Song 003; Arjan Breeschoten; Mario Konijnenburg; Chris Van Hoof; Filip Tavernier; Nick Van Helleputte (IEEE Trans. Biomed. Circuits Syst., 2020)

A 28μW 134dB DR 2nd-Order Noise-Shaping Slope Light-to-Digital Converter for Chest PPG Monitoring. - Qiuyang Lin; Shuang Song 003; Roland Van Wegberg; Mario Konijnenburg; Dwaipayan Biswas; Chris Van Hoof; Filip Tavernier; Nick Van Helleputte (ISSCC, 2021)

A 134 DB Dynamic Range Noise Shaping Slope Light-to-Digital Converter for Wearable Chest PPG Applications. - Qiuyang Lin; Shuang Song 003; Roland Van Wegberg; Wim Sijbers; Dwaipayan Biswas; Mario Konijnenburg; Chris Van Hoof; Filip Tavernier; Nick Van Helleputte (IEEE Trans. Biomed. Circuits Syst., 2021)

A 400-to-12 V Fully Integrated Switched-Capacitor DC-DC Converter Achieving 119 mW/mm2 at 63.6 % Efficiency. - Tuur Van Daele; Filip Tavernier (CICC, 2022)

Photoplethysmography (PPG) Sensor Circuit Design Techniques. - Qiuyang Lin; Christina Avidikou; Filip Tavernier; Nick Van Helleputte (CICC, 2022)

A 240V to 47.5 V Fully Integrated Switched-Capacitor Converter in GaN Achieving 62.6% Efficiency at 220 mW/mm2. - Bram Veraverbeke; Tim Thielemans; Tuur Van Daele; Filip Tavernier (PRIME, 2022)

A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET. - Athanasios Ramkaj; Adalberto Cantoni; Gabriele Manganaro; Siddharth Devarajan; Michiel Steyaert; Filip Tavernier (VLSI Technology and Circuits, 2022)

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity. - Athanasios T. Ramkaj; Marcel J. M. Pelgrom; Michiel S. J. Steyaert; Filip Tavernier (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Multi-Gigahertz Nyquist Analog-to-Digital Converters - Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies, 3 - Athanasios T. Ramkaj; Marcel J. M. Pelgrom; Michiel S. J. Steyaert; Filip Tavernier (Springer, 2023)

A 10 GHz Quadruple-Tail Comparator with Double Feedforward Paths and Minimal Delay Slope in 28 nm CMOS. - Zongyuan Li; Filip Tavernier (ESSCIRC, 2023)

A Fully Integrated 230 VRMS-to-12 VDC AC-DC Converter Achieving 9 mW/mm2. - Tuur Van Daele; Filip Tavernier (VLSI Technology and Circuits, 2023)

Fully Integrating a 400 V-to-12 V DC-DC Converter in High-Voltage CMOS. - Tuur Van Daele; Filip Tavernier (IEEE J. Solid State Circuits, 2023)

A > 70dB Digital Readout Circuit Implemented in 65nm CMOS for 10 $ mu mathrm{m}$ SWIR InGaAs Pixels. - Rico Jossel Maestro; Patrick Merken; Filip Tavernier (IEEE SENSORS, 2024)

Monolithic 230-VRMS-to-12-VDC AC-DC Converter at 9 mW/mm2 Enabled by a 31-325-VDC Input Range Capacitive Multi-Ratio DC-DC Converter. - Tuur Van Daele; Filip Tavernier (IEEE J. Solid State Circuits, 2024)

Guest Editorial IEEE 2023 European Solid-State Circuits Conference. - Filip Tavernier; Danilo Manstretta; Ronan A. R. van der Zee (IEEE J. Solid State Circuits, 2024)

Fully Integrated High-Voltage DC-DC and AC-DC Conversion - Tuur Van Daele; Filip Tavernier (Springer, 2025)

A Digital Jitter Correction Technique For High-Speed ADC-Based Communication Links. - Tim Borremans; Jun Feng; Jonah Van Assche; Georges G. E. Gielen; Filip Tavernier (ISCAS, 2025)

18.8 A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR. - Bram Veraverbeke; Filip Tavernier (ISSCC, 2025)

90 GHz Cryo-CMOS VCO for Enabling High Integration of Quantum Computers. - Pieter-Antonio Fernandez; Faedra Webers; Filip Tavernier; Patrick Reynaert (NewCAS, 2025)

Fully Integrated Optical Injection Locking With Schottky Photodiodes in 65-nm CMOS. - Arnaud Van Mieghem; Michiel Steyaert; Filip Tavernier (IEEE J. Solid State Circuits, 2025)