Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops. - Filippo Minnella; Jordi Cortadella; Mario R. Casu; Mihai T. Lazarescu; Luciano Lavagno (IEEE Access, 2023)

Design and Optimization of Residual Neural Network Accelerators for Low-Power FPGAs Using High-Level Synthesis. - Filippo Minnella; Teodoro Urso; Mihai T. Lazarescu; Luciano Lavagno (CoRR, 2023)

LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. - Roberto Bosio; Giovanni Brignone; Filippo Minnella; M. Usman Jamal; Luciano Lavagno (DATE, 2024)

Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark. - Lorenzo Lagostina; Filippo Minnella; Jordi Cortadella; Mario R. Casu; Mihai T. Lazarescu; Luciano Lavagno (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming. - Roberto Bosio; Filippo Minnella; Teodoro Urso; Mario R. Casu; Luciano Lavagno; Mihai T. Lazarescu; Paolo Pasini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)