Addressing mechanisms for VLIW and superscalar processors. - Fleur L. Steven; Rod Adams; Gordon B. Steven; L. Wang; D. J. Whale (Microprocess. Microprogramming, 1993)

ALU design and processor branch architecture. - Gordon B. Steven; Fleur L. Steven (Microprocess. Microprogramming, 1993)

A superscalar architecture to exploit instruction level parallelism. - Gordon B. Steven; Bruce Christianson; Roger Collins; Richard D. Potter; Fleur L. Steven (Microprocess. Microsystems, 1997)

Static Scheduling for Out-of-order Instruction Issue Processors. - Daniel Tate; Gordon B. Steven; Fleur L. Steven (ACAC, 2000)

Dynamic Branch Prediction Using Neural Networks. - Gordon B. Steven; Rubén Anguera; Colin Egan; Fleur L. Steven; Lucian N. Vintan (DSD, 2001)

Adding static data dependence collapsing to a high-performance instruction scheduler. - Fleur L. Steven; Colin Egan; Richard D. Potter; Gordon B. Steven (J. Syst. Archit., 2001)

Two-level branch prediction using neural networks. - Colin Egan; Gordon B. Steven; Patrick Quick; Rubén Anguera; Fleur L. Steven; Lucian N. Vintan (J. Syst. Archit., 2003)