Analysis of Parallel Algorithms for a Shared Virtual Memory Computer. - Helmut Weberpals; Florent Dupont de Dinechin (PARCO, 1993)

A Localized Parallel Sorting Algorithm and its Implementation. - Helmut Weberpals; Florent Dupont de Dinechin (PARCO, 1995)

Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations. - Florent de Dinechin; Sophie Robert (ASAP, 1996)

A Regular VLSI Array for an Irregular Algorithm. - Florent de Dinechin; Doran Wilde; Sanjay V. Rajopadhye; Rumen Andonov (IRREGULAR, 1996)

Libraries of schedule-free operators in Alpha. - Florent de Dinechin (ASAP, 1997)

Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms. - Florent de Dinechin; Tanguy Risset; Sophie Robert (PARCO, 1997)

A Reconfigurable Engine for Real-Time Video Processing. - Wayne Luk; P. Andreou; Arran Derbyshire; Florent Dupont de Dinechin; J. Rice; Nabeel Shirazi; D. Siganos (FPL, 1998)

Towards Adaptable Hierarchical Placement for FPGAs. - Florent de Dinechin; Wayne Luk; Steve McKeever (FPGA, 1999)

Constant Multipliers for FPGAs. - Florent de Dinechin; Vincent Lefèvre (PDPTA, 2000)

The Price of Routing in FPGAs. - Florent de Dinechin (J. Univers. Comput. Sci., 2000)

Some Improvements on Multipartite Table Methods . - Florent de Dinechin; Arnaud Tisserand (IEEE Symposium on Computer Arithmetic, 2001)

Multipartite Tables in JBits for the Evaluation of Functions on FPGAs. - Jérémie Detrey; Florent de Dinechin (IPDPS, 2002)

Software Carry-Save: A Case Study for Instruction-Level Parallelism. - David Defour; Florent de Dinechin (PaCT, 2003)

Second Order Function Approximation Using a Single Multiplication on FPGAs. - Jérémie Detrey; Florent de Dinechin (FPL, 2004)

Towards the Post-Ultimate libm. - Florent de Dinechin; Alexey V. Ershov; Nicolas Gast (IEEE Symposium on Computer Arithmetic, 2005)

Table-based polynomials for fast hardware function evaluation. - Jérémie Detrey; Florent de Dinechin (ASAP, 2005)

A Parameterized Floating-Point Exponential Function for FPGAs. - Jérémie Detrey; Florent de Dinechin (FPT, 2005)

Multipartite Table Methods. - Florent de Dinechin; Arnaud Tisserand (IEEE Trans. Computers, 2005)

Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. - Jérémie Detrey; Florent de Dinechin (Tech. Sci. Informatiques, 2005)

Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. - Caroline Collange; Jérémie Detrey; Florent de Dinechin (DSD, 2006)

Assisted verification of elementary functions using Gappa. - Florent de Dinechin; Christoph Quirin Lauter; Guillaume Melquiond (SAC, 2006)

Matériel et logiciel pour l'évaluation de fonctions numériques :précision, performance et validation. - Florent de Dinechin (2007)

Return of the hardware floating-point elementary function. - Jérémie Detrey; Florent de Dinechin; Xavier Pujol (IEEE Symposium on Computer Arithmetic, 2007)

Floating-Point Trigonometric Functions for FPGAs. - Jérémie Detrey; Florent de Dinechin (FPL, 2007)

Fast and correctly rounded logarithms in double-precision. - Florent de Dinechin; Christoph Quirin Lauter; Jean-Michel Muller (RAIRO Theor. Informatics Appl., 2007)

Parameterized floating-point logarithm and exponential functions for FPGAs. - Jérémie Detrey; Florent de Dinechin (Microprocess. Microsystems, 2007)

A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic. - Jérémie Detrey; Florent de Dinechin (J. VLSI Signal Process., 2007)

Integer and floating-point constant multipliers for FPGAs. - Nicolas Brisebarre; Florent de Dinechin; Jean-Michel Muller (ASAP, 2008)

FPGA-Based Computation of the Inductance of Coils Used for the Magnetic Stimulation of the Nervous System. - Ionut Trestian; Octavian Cret; Laura Cret; Lucia Vacariu; Radu Tudoran; Florent de Dinechin (BIODEVICES (1), 2008)

When FPGAs are better at floating-point than microprocessors. - Florent de Dinechin; Jérémie Detrey; Octavian Cret; Radu Tudoran (FPGA, 2008)

An FPGA-specific approach to floating-point accumulation and sum-of-products. - Florent de Dinechin; Bogdan Pasca 001; Octavian Cret; Radu Tudoran (FPT, 2008)

Certifying floating-point implementations using Gappa - Florent de Dinechin; Christoph Quirin Lauter; Guillaume Melquiond (CoRR, 2008)

Optimizing polynomials for floating-point implementation - Florent de Dinechin; Christoph Quirin Lauter (CoRR, 2008)

Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. - Jérémie Detrey; Florent de Dinechin (Tech. Sci. Informatiques, 2008)

Digital Arithmetic. - Florent de Dinechin; Milos D. Ercegovac; Jean-Michel Muller; Nathalie Revol (Wiley Encyclopedia of Computer Science and Engineering, 2008)

Generating high-performance custom floating-point pipelines. - Florent de Dinechin; Cristian Klein; Bogdan Pasca 001 (FPL, 2009)

Large multipliers with fewer DSP blocks. - Florent de Dinechin; Bogdan Pasca 001 (FPL, 2009)

Handbook of Floating-Point Arithmetic. - Jean-Michel Muller; Nicolas Brisebarre; Florent de Dinechin; Claude-Pierre Jeannerod; Vincent Lefèvre; Guillaume Melquiond; Nathalie Revol; Damien Stehlé; Serge Torres (Birkhäuser, 2010)

Automatic generation of polynomial-based hardware architectures for function evaluation. - Florent de Dinechin; Mioara Joldes; Bogdan Pasca 001 (ASAP, 2010)

Multiplicative Square Root Algorithms for FPGAs. - Florent de Dinechin; Mioara Joldes; Bogdan Pasca 001; Guillaume Revy (FPL, 2010)

Pipelined FPGA Adders. - Florent de Dinechin; Hong Diep Nguyen; Bogdan Pasca 001 (FPL, 2010)

Floating-point exponential functions for DSP-enabled FPGAs. - Florent de Dinechin; Bogdan Pasca 001 (FPT, 2010)

Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. - Álvaro Vázquez; Florent de Dinechin (FPT, 2010)

LEMA: towards a language for reliable arithmetic. - Vincent Lefèvre; Philippe Théveny; Florent de Dinechin; Claude-Pierre Jeannerod; Christophe Mouilleron; David Pfannholzer; Nathalie Revol (ACM Commun. Comput. Algebra, 2010)

Multipliers for floating-point double precision and beyond on FPGAs. - Sebastian Banescu; Florent de Dinechin; Bogdan Pasca 001; Radu Tudoran (SIGARCH Comput. Archit. News, 2010)

A mixed-precision fused multiply and add. - Nicolas Brunie; Florent de Dinechin; Benoît Dupont de Dinechin (ACSCC, 2011)

The Arithmetic Operators You Will Never See in a Microprocessor. - Florent de Dinechin (IEEE Symposium on Computer Arithmetic, 2011)

An FPGA architecture for solving the Table Maker's Dilemma. - Florent de Dinechin; Jean-Michel Muller; Bogdan Pasca 001; Alexandru Plesco (ASAP, 2011)

Designing Custom Arithmetic Data Paths with FloPoCo. - Florent de Dinechin; Bogdan Pasca 001 (IEEE Des. Test Comput., 2011)

Certifying the Floating-Point Implementation of an Elementary Function Using Gappa. - Florent de Dinechin; Christoph Quirin Lauter; Guillaume Melquiond (IEEE Trans. Computers, 2011)

Table-Based Division by Small Integer Constants. - Florent de Dinechin; Laurent-Stéphane Didier (ARC, 2012)

Multiplication by Rational Constants. - Florent de Dinechin (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Arithmetic core generation using bit heaps. - Nicolas Brunie; Florent de Dinechin; Matei Istoan; Guillaume Sergent; Kinga Illyes; Bogdan Popa (FPL, 2013)

Fixed-point trigonometric functions on FPGAs. - Florent de Dinechin; Matei Istoan; Guillaume Sergent (SIGARCH Comput. Archit. News, 2013)

On Ziv's rounding test. - Florent de Dinechin; Christoph Quirin Lauter; Jean-Michel Muller; Serge Torres (ACM Trans. Math. Softw., 2013)

Floating-Point Exponentiation Units for Reconfigurable Computing. - Florent de Dinechin; Pedro Echeverría; Marisa López-Vallejo; Bogdan Pasca 001 (ACM Trans. Reconfigurable Technol. Syst., 2013)

Sum-of-product architectures computing just right. - Florent de Dinechin; Matei Istoan; Abdelbassat Massouri (ASAP, 2014)

Code Generators for Mathematical Functions. - Nicolas Brunie; Florent de Dinechin; Olga Kupriianova; Christoph Quirin Lauter (ARITH, 2015)

Hardware Implementations of Fixed-Point Atan2. - Florent de Dinechin; Matei Istoan (ARITH, 2015)

Computing floating-point logarithms with fixed-point operations. - Julien Le Maire; Nicolas Brunie; Florent de Dinechin; Jean-Michel Muller (ARITH, 2016)

Automating the pipeline of arithmetic datapaths. - Matei Istoan; Florent de Dinechin (DATE, 2017)

A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. - Yohann Uguen; Florent de Dinechin; Steven Derrien (FCCM, 2017)

Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. - Yohann Uguen; Florent de Dinechin; Steven Derrien (FPL, 2017)

Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT. - Hatam Abdoli; Hooman Nikmehr; Naser Movahedinia; Florent de Dinechin (Circuits Syst. Signal Process., 2017)

Hardware Division by Small Integer Constants. - H. Fatih Ugurdag; Florent de Dinechin; Y. Serhan Gener; Sezer Gören 001; Laurent-Stéphane Didier (IEEE Trans. Computers, 2017)

Handbook of Floating-Point Arithmetic (2nd Ed.). - Jean-Michel Muller; Nicolas Brunie; Florent de Dinechin; Claude-Pierre Jeannerod; Mioara Joldes; Vincent Lefèvre; Guillaume Melquiond; Nathalie Revol; Serge Torres (Springer, 2018)

Karatsuba with Rectangular Multipliers for FPGAs. - Martin Kumm; Oscar Gustafsson; Florent de Dinechin; Johannes Kappauf; Peter Zipf (ARITH, 2018)

Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor. - Andrea Bocco; Yves Durand; Florent de Dinechin (ARITH, 2019)

Reflections on 10 Years of FloPoCo. - Florent de Dinechin (ARITH, 2019)

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. - Florent de Dinechin; Silviu-Ioan Filip; Martin Kumm; Luc Forget (ARITH, 2019)

Evaluating the Hardware Cost of the Posit Number System. - Yohann Uguen; Luc Forget; Florent de Dinechin (FPL, 2019)

A type-safe arbitrary precision arithmetic portability layer for HLS tools. - Luc Forget; Yohann Uguen; Florent de Dinechin; David Thomas 001 (HEART, 2019)

Byte-Aware Floating-point Operations through a UNUM Computing Unit. - Andrea Bocco; Tiago T. Jost; Albert Cohen 001; Florent de Dinechin; Yves Durand; Christian Fabre (VLSI-SoC, 2019)

Guest Editors Introduction: Special Section on Computer Arithmetic. - Javier D. Bruguera; Florent de Dinechin (IEEE Trans. Computers, 2019)

Towards Hardware IIR Filters Computing Just Right: Direct Form I Case Study. - Anastasia Volkova; Matei Istoan; Florent de Dinechin; Thibault Hilaire (IEEE Trans. Computers, 2019)

Next Generation Arithmetic for Edge Computing. - Andre Guntoro; Cecilia De la Parra; Farhad Merchant; Florent de Dinechin; John L. Gustafson; Martin Langhammer; Rainer Leupers; Sangeeth Nambiar (DATE, 2020)

Application-Specific Arithmetic in High-Level Synthesis Tools. - Yohann Uguen; Florent de Dinechin; Victor Lezaud; Steven Derrien (ACM Trans. Archit. Code Optim., 2020)

Resource Optimal Truncated Multipliers for FPGAs. - Andreas Böttcher; Martin Kumm; Florent de Dinechin (ARITH, 2021)

Towards Arithmetic-Centered Filter Design. - Florent de Dinechin; Silviu-Ioan Filip; Martin Kumm; Anastasia Volkova (ARITH, 2021)

Low-precision logarithmic arithmetic for neural network accelerators. - Maxime Christ; Florent de Dinechin; Frédéric Pétrot (ASAP, 2022)

Resource Optimal Squarers for FPGAs. - Andreas Böttcher; Martin Kumm; Florent de Dinechin (FPL, 2022)

Using integer linear programming for correctly rounded multipartite architectures. - Orégane Desrentes; Florent de Dinechin (FPT, 2022)

A single-source C++20 HLS flow for function evaluation on FPGA and beyond. - Luc Forget; Gauthier Harnisch; Ronan Keryell; Florent de Dinechin (HEART, 2022)

Computer Arithmetic: Continuing a Long and Steady Emergence. - Paolo Montuschi; Jean-Michel Muller; Florent de Dinechin (Computer, 2022)

Lossless Differential Table Compression for Hardware Function Evaluation. - Maxime Christ; Luc Forget; Florent de Dinechin (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them. - Anastasia Volkova; Rémi Garcia 002; Florent de Dinechin; Martin Kumm (ACSSC, 2023)

Exact Fused Dot Product Add Operators. - Orégane Desrentes; Benoît Dupont de Dinechin; Florent de Dinechin (ARITH, 2023)

Audio DSP to FPGA Compilation. - Maxime Popoff; Romain Michon; Tanguy Risset; Pierre Cochard; Stéphane Letz; Yann Orlarey; Florent de Dinechin (ASAP, 2023)

Towards Fixed-Point Formats Determination for Faust Programs. - Agathe Herrou; Florent de Dinechin; Stéphane Letz; Yann Orlarey; Anastasia Volkova (CoRR, 2024)

Hardware Fixed-Point 2D and 3D norms. - Romain Bouarah; Florent de Dinechin (ARITH, 2025)

Double-Word Decomposition in a Combined FP16, BF16 and FP32 Dot Product Add Operator. - Orégane Desrentes; Benoît Dupont de Dinechin; Florent de Dinechin (ARITH, 2025)

RETROSPECTIVE: Table-Based Polynomials for Fast Hardware Function Evaluation. - Florent de Dinechin (ASAP, 2025)