FPGA Design of an Open-Loop True Random Number Generator. - Florent Lozach; Molka Ben-Romdhane; Tarik Graba; Jean-Luc Danger (DSD, 2013)

Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA. - Zouha Cherif; Jean-Luc Danger; Florent Lozach; Yves Mathieu; Lilian Bossuet (HASP@ISCA, 2013)

Predictive Aging of Reliability of two Delay PUFs. - Naghmeh Karimi; Jean-Luc Danger; Florent Lozach; Sylvain Guilley (IACR Cryptol. ePrint Arch., 2017)