Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits. - Ion Constatin Tesu; Florentin Dartu (ISCAS, 1993)

A Gate-Delay Model for high-Speed CMOS Circuits. - Florentin Dartu; Noel Menezes; Jessica Qian; Lawrence T. Pillage (DAC, 1994)

RC interconnect synthesis-a moment fitting approach. - Noel Menezes; Satyamurthy Pullela; Florentin Dartu; Lawrence T. Pillage (ICCAD, 1994)

RC-Interconnect Macromodels for Timing Simulation. - Florentin Dartu; Bogdan Tutuianu; Lawrence T. Pileggi (DAC, 1996)

An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. - Bogdan Tutuianu; Florentin Dartu; Lawrence T. Pileggi (DAC, 1996)

Performance computation for precharacterized CMOS gates with RC loads. - Florentin Dartu; Noel Menezes; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. - Florentin Dartu; Lawrence T. Pileggi (DAC, 1997)

CMOS Gate Delay Models for General RLC Loading. - Ravishankar Arunachalam; Florentin Dartu; Lawrence T. Pileggi (ICCD, 1997)

TETA: Transistor-Level Engine for Timing Analysis. - Florentin Dartu; Lawrence T. Pileggi (DAC, 1998)

Timed pattern generation for noise-on-delay calculation. - Seung Hoon Choi; Kaushik Roy 001; Florentin Dartu (DAC, 2002)

TETA: transistor-level waveform evaluation for timing analysis. - Emrah Acar; Florentin Dartu; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Statistical gate delay model considering multiple input switching. - Aseem Agarwal; Florentin Dartu; David T. Blaauw (DAC, 2004)

Modeling unbuffered latches for timing analysis. - Chirayu S. Amin; Florentin Dartu; Yehea I. Ismail (ICCAD, 2004)

Piece-wise approximations of RLCK circuit responses using moment matching. - Chirayu S. Amin; Yehea I. Ismail; Florentin Dartu (DAC, 2005)

Statistical static timing analysis: how simple can we get? - Chirayu S. Amin; Noel Menezes; Kip Killpack; Florentin Dartu; Umakanta Choudhury; Nagib Hakim; Yehea I. Ismail (DAC, 2005)

Variability modeling and variability-aware design in deep submicron integrated circuits. - Florentin Dartu; Anirudh Devgan; Noel Menezes (ACM Great Lakes Symposium on VLSI, 2005)

Expanding the frequency range of AWE via time shifting. - Ahmed M. Shebaita; Chirayu S. Amin; Florentin Dartu; Yehea I. Ismail (ICCAD, 2005)

Weibull-based analytical waveform model. - Chirayu S. Amin; Florentin Dartu; Yehea I. Ismail (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Algorithms for MIS vector generation and pruning. - Kenneth S. Stevens; Florentin Dartu (ICCAD, 2006)

Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching. - Seung Hoon Choi; Kunhyuk Kang; Florentin Dartu; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

To do or not to do hierarchical timing? - Florentin Dartu; Qiuyang Wu (ISPD, 2013)